patch 'event/cnxk: fix CASP usage for clang' has been queued to stable release 22.11.4

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 22.11.4

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/15/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=15b1bc964b4e369724224f0b6cf3737341ad0cd3

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 15b1bc964b4e369724224f0b6cf3737341ad0cd3 Mon Sep 17 00:00:00 2001
From: Pavan Nikhilesh <pbhagavatula at marvell.com>
Date: Mon, 24 Jul 2023 14:11:56 +0530
Subject: [PATCH] event/cnxk: fix CASP usage for clang
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 694e8e643de3c763216bb5cc187fb9be0c520f92 ]

Clang fails to use register pairs for CASP instruction, use
inline asm to fix register pairs.

Fixes: e239e0d3faf7 ("event/cnxk: add SSO HW device operations")

Signed-off-by: Pavan Nikhilesh <pbhagavatula at marvell.com>
---
 drivers/event/cnxk/cn10k_worker.h | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h
index a93d40ed40..1bce0631e5 100644
--- a/drivers/event/cnxk/cn10k_worker.h
+++ b/drivers/event/cnxk/cn10k_worker.h
@@ -300,19 +300,32 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
 	} gw;

 	gw.get_work = ws->gw_wdata;
-#if defined(RTE_ARCH_ARM64) && !defined(__clang__)
+#if defined(RTE_ARCH_ARM64)
+#if !defined(__clang__)
 	asm volatile(
 		PLT_CPU_FEATURE_PREAMBLE
 		"caspal %[wdata], %H[wdata], %[wdata], %H[wdata], [%[gw_loc]]\n"
 		: [wdata] "+r"(gw.get_work)
 		: [gw_loc] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0)
 		: "memory");
+#else
+	register uint64_t x0 __asm("x0") = (uint64_t)gw.u64[0];
+	register uint64_t x1 __asm("x1") = (uint64_t)gw.u64[1];
+	asm volatile(".arch armv8-a+lse\n"
+		     "caspal %[x0], %[x1], %[x0], %[x1], [%[dst]]\n"
+		     : [x0] "+r"(x0), [x1] "+r"(x1)
+		     : [dst] "r"(ws->base + SSOW_LF_GWS_OP_GET_WORK0)
+		     : "memory");
+	gw.u64[0] = x0;
+	gw.u64[1] = x1;
+#endif
 #else
 	plt_write64(gw.u64[0], ws->base + SSOW_LF_GWS_OP_GET_WORK0);
 	do {
 		roc_load_pair(gw.u64[0], gw.u64[1],
 			      ws->base + SSOW_LF_GWS_WQE0);
 	} while (gw.u64[0] & BIT_ULL(63));
+	rte_atomic_thread_fence(__ATOMIC_SEQ_CST);
 #endif
 	ws->gw_rdata = gw.u64[0];
 	if (gw.u64[1])
--
2.25.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-10-22 22:17:36.439761700 +0800
+++ 0055-event-cnxk-fix-CASP-usage-for-clang.patch	2023-10-22 22:17:34.266723700 +0800
@@ -1 +1 @@
-From 694e8e643de3c763216bb5cc187fb9be0c520f92 Mon Sep 17 00:00:00 2001
+From 15b1bc964b4e369724224f0b6cf3737341ad0cd3 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 694e8e643de3c763216bb5cc187fb9be0c520f92 ]
@@ -10 +12,0 @@
-Cc: stable at dpdk.org
@@ -18 +20 @@
-index 46bfa9dd9d..30290ddd06 100644
+index a93d40ed40..1bce0631e5 100644
@@ -21 +23 @@
-@@ -249,19 +249,32 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,
+@@ -300,19 +300,32 @@ cn10k_sso_hws_get_work(struct cn10k_sso_hws *ws, struct rte_event *ev,