patch 'net/mlx5/hws: enable multiple integrity items' has been queued to stable release 22.11.5

[luca.boccassi at gmail.com]

Hi,

FYI, your patch has been queued to stable release 22.11.5

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 03/16/24. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/bluca/dpdk-stable

This queued commit can be viewed at:
https://github.com/bluca/dpdk-stable/commit/325c88d078153ecc36f5dab892a5a8396e5f6cde

Thanks.

Luca Boccassi

---
>From 325c88d078153ecc36f5dab892a5a8396e5f6cde Mon Sep 17 00:00:00 2001
From: Michael Baum <michaelba at nvidia.com>
Date: Wed, 28 Feb 2024 11:50:55 +0200
Subject: [PATCH] net/mlx5/hws: enable multiple integrity items

[ upstream commit 8c178ac8ce81ab0cbd9e90fd7eb4a2b47fca7c2b ]

The integrity item uses the DW "oks1" in header layout. It includes the
all supported bits for both inner and outer. When item is integrity
type, the relevant bits are turned on and all DW is submitted.

When user provides more then single integrity item in same pattern, the
last one overrides the values were submitted before. This is problematic
when user wants to match integrity bits for both inner and outer in same
pattern, he cannot merge them into single item since rte_flow API
provides encapsulation level field to match either inner or outer.

This patch avoids the overriding values, when "oks1" is submitted,
operator "or" is used instead of regular set.

Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")

Signed-off-by: Michael Baum <michaelba at nvidia.com>
Reviewed-by: Erez Shitrit <erezsh at nvidia.com>
Acked-by: Matan Azrad <matan at nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index b3d8d9504e..d81d66523a 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -31,6 +31,10 @@
 				  (bit_off))); \
 	} while (0)
 
+/* Getter function based on bit offset and mask, for 32bit DW*/
+#define DR_GET_32(p, byte_off, bit_off, mask) \
+	((rte_be_to_cpu_32(*((const rte_be32_t *)(p) + ((byte_off) / 4))) >> (bit_off)) & (mask))
+
 /* Setter function based on bit offset and mask */
 #define DR_SET(p, v, byte_off, bit_off, mask) \
 	do { \
@@ -271,7 +275,7 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,
 {
 	bool inner = (fc->fname == MLX5DR_DEFINER_FNAME_INTEGRITY_I);
 	const struct rte_flow_item_integrity *v = item_spec;
-	uint32_t ok1_bits = 0;
+	uint32_t ok1_bits = DR_GET_32(tag, fc->byte_off, fc->bit_off, fc->bit_mask);
 
 	if (v->l3_ok)
 		ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) |
-- 
2.39.2

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2024-03-14 00:09:22.882320867 +0000
+++ 0047-net-mlx5-hws-enable-multiple-integrity-items.patch	2024-03-14 00:09:20.681616571 +0000
@@ -1 +1 @@
-From 8c178ac8ce81ab0cbd9e90fd7eb4a2b47fca7c2b Mon Sep 17 00:00:00 2001
+From 325c88d078153ecc36f5dab892a5a8396e5f6cde Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit 8c178ac8ce81ab0cbd9e90fd7eb4a2b47fca7c2b ]
+
@@ -20 +21,0 @@
-Cc: stable at dpdk.org
@@ -30 +31 @@
-index e036aca781..0e15aafb8a 100644
+index b3d8d9504e..d81d66523a 100644
@@ -33 +34 @@
-@@ -44,6 +44,10 @@
+@@ -31,6 +31,10 @@
@@ -44 +45 @@
-@@ -509,7 +513,7 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,
+@@ -271,7 +275,7 @@ mlx5dr_definer_integrity_set(struct mlx5dr_definer_fc *fc,
@@ -52 +53 @@
- 		ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) :
+ 		ok1_bits |= inner ? BIT(MLX5DR_DEFINER_OKS1_SECOND_L3_OK) |