[dpdk-users] DPDK IP Pipeline query

[Singh, Jasvinder]

Hi Biju,

Please see inline.

> -----Original Message-----
> From: users [mailto:users-bounces at dpdk.org] On Behalf Of Talukdar, Biju
> Sent: Wednesday, May 4, 2016 4:09 PM
> To: users <users at dpdk.org>
> Subject: [dpdk-users] DPDK IP Pipeline query
> 
> Hi,
> 
> 
> I have one question regarding DPDK IP Pipeline. We are trying to use multiple
> cores and multiple queues using PASS-THROUGH pipeline. We have one
> input port RXQ0 and a output port TXQ0. Now we want to use several cores
> to process  the incoming traffic. We want to instantiate several pipelines and
> pin them to different cores. But we are not able to figure out how the
> configuration files should look like. Please see the following configuration file
> we tried. It gave us error saying more than one writer .
> 
> 
> Then we thought we could use RX0.1 and TX0.1. We got the error saying
> LINK0 RXQs are not contiguous (B).
> 
> 
> Our goal is to use more cores for the incoming traffic from the same port.
> 

For distributing the incoming traffic across multiple queues of the nic port, you can use RSS feature. We have recently submitted the patch (link below) on the mailing list for consideration in dpdk16.07 release. 
http://dpdk.org/dev/patchwork/patch/12300/

Please apply the patch and use following configuration to get traffic on different queues of the nic port.

[PIPELINE0]
type = MASTER
core = 0

[LINK0]
rss_qs = 0 1

[PIPELINE1]
type = PASS-THROUGH
core = 1
pktq_in = RXQ0.0  RXQ0.1       
pktq_out = SWQ0 SWQ1

[PIPELINE2]
type = PASS-THROUGH
core = 2
pktq_in = SWQ0        
pktq_out = TXQ0.0

[PIPELINE3]
type = PASS-THROUGH
core = 3
pktq_in = SWQ1        
pktq_out = TXQ1.0

 
Thanks,
Jasvinder

> sample configuration file
> 
> 
> [PIPELINE0]
> type = MASTER
> core = 0
> 
> [PIPELINE1]
> type = PASS-THROUGH
> core = 1
> pktq_in = RXQ0.0
> pktq_out = SWQ0 SWQ1
> dma_size = 16
> dma_dst_offset = 128; mbuf (128) + 64
> dma_src_offset = 278; mbuf (128) + headroom (128) + ethernet header (14)
> + ttl offset within ip header (8) = 278 dma_src_mask =
> 00FF0000FFFFFFFFFFFFFFFFFFFFFFFF; ipv4 5-tuple dma_hash_offset = 144;
> dma_dst_offset + dma_size
> 
> 
> [PIPELINE2]
> type = PASS-THROUGH
> core = 2
> pktq_in = SWQ0
> pktq_out = TXQ0.0
> dma_size = 16
> dma_dst_offset = 128; mbuf (128) + 64
> dma_src_offset = 278; mbuf (128) + headroom (128) + ethernet header (14)
> + ttl offset within ip header (8) = 278 dma_src_mask =
> 00FF0000FFFFFFFFFFFFFFFFFFFFFFFF; ipv4 5-tuple dma_hash_offset = 144;
> dma_dst_offset + dma_size
> 
> 
> [PIPELINE3]
> type = PASS-THROUGH
> core = 3
> pktq_in = SWQ1
> pktq_out = TXQ0.0
> dma_size = 16
> dma_dst_offset = 128; mbuf (128) + 64
> dma_src_offset = 278; mbuf (128) + headroom (128) + ethernet header (14)
> + ttl offset within ip header (8) = 278 dma_src_mask =
> 00FF0000FFFFFFFFFFFFFFFFFFFFFFFF; ipv4 5-tuple dma_hash_offset = 144;
> dma_dst_offset + dma_size
> 
> 
> 
> Thank you
> 
> Biju