[dpdk-dev] doc: update release notes for I/O device memory access API

Message ID 1484804601-26531-1-git-send-email-jerin.jacob@caviumnetworks.com (mailing list archive)
State Accepted, archived
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel compilation success Compilation OK

Commit Message

Jerin Jacob Jan. 19, 2017, 5:43 a.m. UTC
  Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
---
 doc/guides/rel_notes/release_17_02.rst | 13 +++++++++++++
 1 file changed, 13 insertions(+)
  

Comments

John McNamara Jan. 19, 2017, 5:35 p.m. UTC | #1
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Jerin Jacob
> Sent: Thursday, January 19, 2017 5:43 AM
> To: dev@dpdk.org
> Cc: thomas.monjalon@6wind.com; Jerin Jacob
> <jerin.jacob@caviumnetworks.com>
> Subject: [dpdk-dev] [PATCH] doc: update release notes for I/O device
> memory access API
> 
> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>


Acked-by: John McNamara <john.mcnamara@intel.com>
  
Thomas Monjalon Jan. 30, 2017, 6:02 p.m. UTC | #2
> > Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
> 
> Acked-by: John McNamara <john.mcnamara@intel.com>

Applied, thanks
  

Patch

diff --git a/doc/guides/rel_notes/release_17_02.rst b/doc/guides/rel_notes/release_17_02.rst
index 0ecd720..eb0e3c0 100644
--- a/doc/guides/rel_notes/release_17_02.rst
+++ b/doc/guides/rel_notes/release_17_02.rst
@@ -193,6 +193,19 @@  New Features
   See the :ref:`Elastic Flow Distributor Library <Efd_Library>` documentation in
   the Programmers Guide document, for more information.
 
+* **Added generic EAL API for I/O device memory read/write operations.**
+
+  This API introduces 8-bit, 16-bit, 32bit, 64bit I/O device
+  memory read/write operations along with the relaxed versions.
+
+  The weakly-ordered machine like ARM needs additional I/O barrier for
+  device memory read/write access over PCI bus.
+  By introducing the EAL abstraction for I/O device memory read/write access,
+  The drivers can access I/O device memory in architecture-agnostic manner.
+  The relaxed version does not have additional I/O memory barrier, useful in
+  accessing the device registers of integrated controllers which
+  implicitly strongly ordered with respect to memory access.
+
 
 Resolved Issues
 ---------------