[dpdk-dev,RFC] ring: relax alignment constraint on ring structure

  The initial objective of
commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting")
was to add an empty cache line betwee, the producer and consumer
data (on platform with cache line size = 64B), preventing from
having them on adjacent cache lines.

Following discussion on the mailing list, it appears that this
also imposes an alignment constraint that is not required.

This patch removes the extra alignment constraint and adds the
empty cache lines using padding fields in the structure. The
size of rte_ring structure and the offset of the fields remain
the same on platforms with cache line size = 64B:

  rte_ring = 384
  rte_ring.name = 0
  rte_ring.flags = 32
  rte_ring.memzone = 40
  rte_ring.size = 48
  rte_ring.mask = 52
  rte_ring.prod = 128
  rte_ring.cons = 256

But it has an impact on platform where cache line size is 128B:

  rte_ring = 384        -> 768
  rte_ring.name = 0
  rte_ring.flags = 32
  rte_ring.memzone = 40
  rte_ring.size = 48
  rte_ring.mask = 52
  rte_ring.prod = 128   -> 256
  rte_ring.cons = 256   -> 512

Link: http://dpdk.org/dev/patchwork/patch/25039/
Suggested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
---

I'm sending this patch to throw the discussion again, but since it
breaks the ABI on platform with cache lines = 128B, I think we should
follow the usual ABI breakage process.

If everybody agree, I'll send a notice and resend a similar patch after
17.08.

Olivier



 lib/librte_ring/rte_ring.h | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)
  

Hi,

On Fri, 30 Jun 2017 16:26:09 +0200, Olivier Matz <olivier.matz@6wind.com> wrote:
> The initial objective of
> commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting")
> was to add an empty cache line betwee, the producer and consumer
> data (on platform with cache line size = 64B), preventing from
> having them on adjacent cache lines.
> 
> Following discussion on the mailing list, it appears that this
> also imposes an alignment constraint that is not required.
> 
> This patch removes the extra alignment constraint and adds the
> empty cache lines using padding fields in the structure. The
> size of rte_ring structure and the offset of the fields remain
> the same on platforms with cache line size = 64B:
> 
>   rte_ring = 384
>   rte_ring.name = 0
>   rte_ring.flags = 32
>   rte_ring.memzone = 40
>   rte_ring.size = 48
>   rte_ring.mask = 52
>   rte_ring.prod = 128
>   rte_ring.cons = 256
> 
> But it has an impact on platform where cache line size is 128B:
> 
>   rte_ring = 384        -> 768
>   rte_ring.name = 0
>   rte_ring.flags = 32
>   rte_ring.memzone = 40
>   rte_ring.size = 48
>   rte_ring.mask = 52
>   rte_ring.prod = 128   -> 256
>   rte_ring.cons = 256   -> 512
> 
> Link: http://dpdk.org/dev/patchwork/patch/25039/
> Suggested-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
> Signed-off-by: Olivier Matz <olivier.matz@6wind.com>
> ---
> 
> I'm sending this patch to throw the discussion again, but since it
> breaks the ABI on platform with cache lines = 128B, I think we should
> follow the usual ABI breakage process.
> 
> If everybody agree, I'll send a notice and resend a similar patch after
> 17.08.
> 

If there is no comment, I'll send a deprecation notice in the
coming days.

Thanks,
Olivier