[dpdk-dev,v3,3/3] mlx4,5: handle 32 bit PCI domain

Message ID 20170705165533.20581-4-stephen@networkplumber.org (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers

Checks

Context Check Description
ci/checkpatch warning coding style issues
ci/Intel-compilation success Compilation OK

Commit Message

Stephen Hemminger July 5, 2017, 4:55 p.m. UTC
  The PCI domain in Azure maybe 32 bits. When device is passed through
the domain is synthesize from the internal GUID. The code that
parses for PCI address in Mellanox drivers needs to use wider
scanf format.

Signed-off-by: Stephen Hemminger <sthemmin@microsoft.com>
---
v3 - add MLX4

 drivers/net/mlx4/mlx4.c        | 2 +-
 drivers/net/mlx5/mlx5_ethdev.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)
  

Patch

diff --git a/drivers/net/mlx4/mlx4.c b/drivers/net/mlx4/mlx4.c
index 16cafae7d741..902a669c923a 100644
--- a/drivers/net/mlx4/mlx4.c
+++ b/drivers/net/mlx4/mlx4.c
@@ -5239,7 +5239,7 @@  mlx4_ibv_device_to_pci_addr(const struct ibv_device *device,
 		/* Extract information. */
 		if (sscanf(line,
 			   "PCI_SLOT_NAME="
-			   "%" SCNx16 ":%" SCNx8 ":%" SCNx8 ".%" SCNx8 "\n",
+			   "%" SCNx32 ":%" SCNx8 ":%" SCNx8 ".%" SCNx8 "\n",
 			   &pci_addr->domain,
 			   &pci_addr->bus,
 			   &pci_addr->devid,
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c
index 96bccd5fd201..039335e2e470 100644
--- a/drivers/net/mlx5/mlx5_ethdev.c
+++ b/drivers/net/mlx5/mlx5_ethdev.c
@@ -1185,7 +1185,7 @@  mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
 		/* Extract information. */
 		if (sscanf(line,
 			   "PCI_SLOT_NAME="
-			   "%" SCNx16 ":%" SCNx8 ":%" SCNx8 ".%" SCNx8 "\n",
+			   "%" SCNx32 ":%" SCNx8 ":%" SCNx8 ".%" SCNx8 "\n",
 			   &pci_addr->domain,
 			   &pci_addr->bus,
 			   &pci_addr->devid,