diff mbox

[dpdk-dev,v4,8/8] net/mlx4: mitigate Tx path memory barriers

Message ID 1509474093-31388-9-git-send-email-matan@mellanox.com (mailing list archive)
State Superseded, archived
Delegated to: Ferruh Yigit
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Matan Azrad Oct. 31, 2017, 6:21 p.m. UTC 
  Replace most of the memory barriers by IO memory barriers since they
are all targeted to the DRAM; This improves code efficiency for
systems which force store order between different addresses.

Only the doorbell register store should be protected by memory barrier
since it is targeted to the PCI memory domain.

Limit pre byte count store IO memory barrier for systems with cache
line size smaller than 64B (TXBB size).

This patch improves Tx performance by 0.2MPPS for one segment 64B
packets via 1 queue with 1 core test.

Signed-off-by: Matan Azrad <matan@mellanox.com>
---
 drivers/net/mlx4/mlx4_rxtx.c | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

Comments

Adrien Mazarguil Nov. 2, 2017, 1:43 p.m. UTC | #1 
On Tue, Oct 31, 2017 at 06:21:33PM +0000, Matan Azrad wrote:
> Replace most of the memory barriers by IO memory barriers since they
> are all targeted to the DRAM; This improves code efficiency for
> systems which force store order between different addresses.
> 
> Only the doorbell register store should be protected by memory barrier
> since it is targeted to the PCI memory domain.
> 
> Limit pre byte count store IO memory barrier for systems with cache
> line size smaller than 64B (TXBB size).
> 
> This patch improves Tx performance by 0.2MPPS for one segment 64B
> packets via 1 queue with 1 core test.
> 
> Signed-off-by: Matan Azrad <matan@mellanox.com>

Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
diff mbox

Patch

diff --git a/drivers/net/mlx4/mlx4_rxtx.c b/drivers/net/mlx4/mlx4_rxtx.c
index bd6d888..fc7a922 100644
--- a/drivers/net/mlx4/mlx4_rxtx.c
+++ b/drivers/net/mlx4/mlx4_rxtx.c
@@ -169,7 +169,7 @@  struct pv {
 		/*
 		 * Make sure we read the CQE after we read the ownership bit.
 		 */
-		rte_rmb();
+		rte_io_rmb();
 #ifndef NDEBUG
 		if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
 			     MLX4_CQE_OPCODE_ERROR)) {
@@ -197,14 +197,9 @@  struct pv {
 	} while (1);
 	if (unlikely(pkts == 0))
 		return 0;
-	/*
-	 * Update CQ.
-	 * To prevent CQ overflow we first update CQ consumer and only then
-	 * the ring consumer.
-	 */
+	/* Update CQ. */
 	cq->cons_index = cons_index;
 	*cq->set_ci_db = rte_cpu_to_be_32(cq->cons_index & MLX4_CQ_DB_CI_MASK);
-	rte_wmb();
 	sq->tail = sq->tail + nr_txbbs;
 	/* Update the list of packets posted for transmission. */
 	elts_comp -= pkts;
@@ -321,6 +316,7 @@  struct pv {
 		 * control segment.
 		 */
 		if ((uintptr_t)dseg & (uintptr_t)(MLX4_TXBB_SIZE - 1)) {
+#if RTE_CACHE_LINE_SIZE < 64
 			/*
 			 * Need a barrier here before writing the byte_count
 			 * fields to make sure that all the data is visible
@@ -331,6 +327,7 @@  struct pv {
 			 * data, and end up sending the wrong data.
 			 */
 			rte_io_wmb();
+#endif /* RTE_CACHE_LINE_SIZE */
 			dseg->byte_count = byte_count;
 		} else {
 			/*
@@ -471,8 +468,7 @@  struct pv {
 				break;
 			}
 #endif /* NDEBUG */
-			/* Need a barrier here before byte count store. */
-			rte_io_wmb();
+			/* Never be TXBB aligned, no need compiler barrier. */
 			dseg->byte_count = rte_cpu_to_be_32(buf->data_len);
 			/* Fill the control parameters for this packet. */
 			ctrl->fence_size = (WQE_ONE_DATA_SEG_SIZE >> 4) & 0x3f;
@@ -534,7 +530,7 @@  struct pv {
 		 * setting ownership bit (because HW can start
 		 * executing as soon as we do).
 		 */
-		rte_wmb();
+		rte_io_wmb();
 		ctrl->owner_opcode = rte_cpu_to_be_32(owner_opcode |
 					      ((sq->head & sq->txbb_cnt) ?
 						       MLX4_BIT_WQE_OWN : 0));