[dpdk-dev,v2] igb_uio: allow multi-process access
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Commit Message
In some case, one device are accessed by different processes via
different BARs, so one uio device may be opened by more than one
process, for this case we just need to enable interrupt once, and
pci_clear_master only when the last process closed.
Fixes: 5f6ff30dc507 ("igb_uio: fix interrupt enablement after FLR in VM")
Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
---
v2:
- Make uio reference counter operation atomic.
---
lib/librte_eal/linuxapp/igb_uio/igb_uio.c | 9 +++++++++
1 file changed, 9 insertions(+)
Comments
Hi,
On Tue, Dec 19, 2017 at 07:42:20AM -0800, Xiao Wang wrote:
> @@ -336,6 +337,10 @@ struct rte_uio_pci_dev {
> struct pci_dev *dev = udev->pdev;
> int err;
>
> + atomic_inc(&udev->refcnt);
> + if (atomic_read(&udev->refcnt) > 1)
The "inc and read" should be atomic. Otherwise below
sequence may happen:
P1: atomic_inc(&udev->refcnt);
P2: atomic_inc(&udev->refcnt);
P1: if (atomic_read(&udev->refcnt) > 1)
P2: if (atomic_read(&udev->refcnt) > 1)
> + return 0;
> +
> /* set bus master, which was cleared by the reset function */
> pci_set_master(dev);
>
> @@ -354,6 +359,10 @@ struct rte_uio_pci_dev {
> struct rte_uio_pci_dev *udev = info->priv;
> struct pci_dev *dev = udev->pdev;
>
> + atomic_dec(&udev->refcnt);
> + if (atomic_read(&udev->refcnt) > 0)
> + return 0;
Ditto.
Best regards,
Tiwei Bie
> +
> /* disable interrupts */
> igbuio_pci_disable_interrupts(udev);
>
> --
> 1.8.3.1
>
Thanks for pointing it out. Fix it in v3.
BRs,
Xiao
> -----Original Message-----
> From: Bie, Tiwei
> Sent: Tuesday, December 19, 2017 5:05 PM
> To: Wang, Xiao W <xiao.w.wang@intel.com>
> Cc: Yigit, Ferruh <ferruh.yigit@intel.com>; dev@dpdk.org;
> stephen@networkplumber.org
> Subject: Re: [dpdk-dev] [PATCH v2] igb_uio: allow multi-process access
>
> Hi,
>
> On Tue, Dec 19, 2017 at 07:42:20AM -0800, Xiao Wang wrote:
> > @@ -336,6 +337,10 @@ struct rte_uio_pci_dev {
> > struct pci_dev *dev = udev->pdev;
> > int err;
> >
> > + atomic_inc(&udev->refcnt);
> > + if (atomic_read(&udev->refcnt) > 1)
>
> The "inc and read" should be atomic. Otherwise below
> sequence may happen:
>
> P1: atomic_inc(&udev->refcnt);
> P2: atomic_inc(&udev->refcnt);
> P1: if (atomic_read(&udev->refcnt) > 1)
> P2: if (atomic_read(&udev->refcnt) > 1)
>
> > + return 0;
> > +
> > /* set bus master, which was cleared by the reset function */
> > pci_set_master(dev);
> >
> > @@ -354,6 +359,10 @@ struct rte_uio_pci_dev {
> > struct rte_uio_pci_dev *udev = info->priv;
> > struct pci_dev *dev = udev->pdev;
> >
> > + atomic_dec(&udev->refcnt);
> > + if (atomic_read(&udev->refcnt) > 0)
> > + return 0;
>
> Ditto.
>
> Best regards,
> Tiwei Bie
>
> > +
> > /* disable interrupts */
> > igbuio_pci_disable_interrupts(udev);
> >
> > --
> > 1.8.3.1
> >
On Tue, 19 Dec 2017 07:42:20 -0800
Xiao Wang <xiao.w.wang@intel.com> wrote:
> + atomic_dec(&udev->refcnt);
> + if (atomic_read(&udev->refcnt) > 0)
> + return 0;
> +
The point of using atomic functions is to do atomic operations.
You need to use atomic_dec_and_test here.
@@ -45,6 +45,7 @@ struct rte_uio_pci_dev {
struct uio_info info;
struct pci_dev *pdev;
enum rte_intr_mode mode;
+ atomic_t refcnt;
};
static char *intr_mode;
@@ -336,6 +337,10 @@ struct rte_uio_pci_dev {
struct pci_dev *dev = udev->pdev;
int err;
+ atomic_inc(&udev->refcnt);
+ if (atomic_read(&udev->refcnt) > 1)
+ return 0;
+
/* set bus master, which was cleared by the reset function */
pci_set_master(dev);
@@ -354,6 +359,10 @@ struct rte_uio_pci_dev {
struct rte_uio_pci_dev *udev = info->priv;
struct pci_dev *dev = udev->pdev;
+ atomic_dec(&udev->refcnt);
+ if (atomic_read(&udev->refcnt) > 0)
+ return 0;
+
/* disable interrupts */
igbuio_pci_disable_interrupts(udev);