diff mbox series

mem: fix DMA mask width sanity check

Message ID 20181107094456.23123-1-alejandro.lucero@netronome.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series mem: fix DMA mask width sanity check |

Checks

Context Check Description
ci/checkpatch warning coding style issues
ci/Intel-compilation success Compilation OK
ci/intel-Performance-Testing success Performance Testing PASS
ci/mellanox-Performance-Testing success Performance Testing PASS

Commit Message

Alejandro Lucero Nov. 7, 2018, 9:44 a.m. UTC 
  Current code has different max DMA mask width values for 32 and 64
bits systems. IOMMU hardware could report a higher supported width
than current MAX_DMA_MASK_BITS when RTE_ARCH_64 is not defined. This
is actually true with a 32 bits kernel running in a 64 bits server
with IOMMU hardware. This could also be a problem with embedded systems
using an IOMMU designed for 64 bits in a 32 bits system.

This patch leaves a single max DMA mask width which will make sure the
mask width is within the range for 64 bits variables used for DMA mask.
This also will avoid wrong values because any value higher than
64 bits is likely wrong.

Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
---
 lib/librte_eal/common/eal_common_memory.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

Comments

Anatoly Burakov Nov. 7, 2018, 10:14 a.m. UTC | #1 
On 07-Nov-18 9:44 AM, Alejandro Lucero wrote:
> Current code has different max DMA mask width values for 32 and 64
> bits systems. IOMMU hardware could report a higher supported width
> than current MAX_DMA_MASK_BITS when RTE_ARCH_64 is not defined. This
> is actually true with a 32 bits kernel running in a 64 bits server
> with IOMMU hardware. This could also be a problem with embedded systems
> using an IOMMU designed for 64 bits in a 32 bits system.
> 
> This patch leaves a single max DMA mask width which will make sure the
> mask width is within the range for 64 bits variables used for DMA mask.
> This also will avoid wrong values because any value higher than
> 64 bits is likely wrong.
> 
> Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
> ---

Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
Ferruh Yigit Nov. 7, 2018, 11:47 a.m. UTC | #2 
On 11/7/2018 10:14 AM, Burakov, Anatoly wrote:
> On 07-Nov-18 9:44 AM, Alejandro Lucero wrote:
>> Current code has different max DMA mask width values for 32 and 64
>> bits systems. IOMMU hardware could report a higher supported width
>> than current MAX_DMA_MASK_BITS when RTE_ARCH_64 is not defined. This
>> is actually true with a 32 bits kernel running in a 64 bits server
>> with IOMMU hardware. This could also be a problem with embedded systems
>> using an IOMMU designed for 64 bits in a 32 bits system.
>>
>> This patch leaves a single max DMA mask width which will make sure the
>> mask width is within the range for 64 bits variables used for DMA mask.
>> This also will avoid wrong values because any value higher than
>> 64 bits is likely wrong.
>>
>> Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
>> ---
> 
> Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>

Tested-by: Ferruh Yigit <ferruh.yigit@intel.com>
Thomas Monjalon Nov. 7, 2018, 1:43 p.m. UTC | #3 
07/11/2018 12:47, Ferruh Yigit:
> On 11/7/2018 10:14 AM, Burakov, Anatoly wrote:
> > On 07-Nov-18 9:44 AM, Alejandro Lucero wrote:
> >> Current code has different max DMA mask width values for 32 and 64
> >> bits systems. IOMMU hardware could report a higher supported width
> >> than current MAX_DMA_MASK_BITS when RTE_ARCH_64 is not defined. This
> >> is actually true with a 32 bits kernel running in a 64 bits server
> >> with IOMMU hardware. This could also be a problem with embedded systems
> >> using an IOMMU designed for 64 bits in a 32 bits system.
> >>
> >> This patch leaves a single max DMA mask width which will make sure the
> >> mask width is within the range for 64 bits variables used for DMA mask.
> >> This also will avoid wrong values because any value higher than
> >> 64 bits is likely wrong.
> >>
> >> Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
> >> ---
> > 
> > Acked-by: Anatoly Burakov <anatoly.burakov@intel.com>
> 
> Tested-by: Ferruh Yigit <ferruh.yigit@intel.com>

Fixes: 223b7f1d5ef6 ("mem: add function for checking memseg IOVA")

Applied, thanks
diff mbox series

Patch

diff --git a/lib/librte_eal/common/eal_common_memory.c b/lib/librte_eal/common/eal_common_memory.c
index 87fd9921f..d47ea4938 100644
--- a/lib/librte_eal/common/eal_common_memory.c
+++ b/lib/librte_eal/common/eal_common_memory.c
@@ -439,11 +439,7 @@  check_iova(const struct rte_memseg_list *msl __rte_unused,
 	return 1;
 }
 
-#if defined(RTE_ARCH_64)
 #define MAX_DMA_MASK_BITS 63
-#else
-#define MAX_DMA_MASK_BITS 31
-#endif
 
 /* check memseg iovas are within the required range based on dma mask */
 static int __rte_experimental
@@ -453,7 +449,8 @@  check_dma_mask(uint8_t maskbits, bool thread_unsafe)
 	uint64_t mask;
 	int ret;
 
-	/* sanity check */
+	/* Sanity check. We only check width can be managed with 64 bits
+	 * variables. Indeed any higher value is likely wrong. */
 	if (maskbits > MAX_DMA_MASK_BITS) {
 		RTE_LOG(ERR, EAL, "wrong dma mask size %u (Max: %u)\n",
 				   maskbits, MAX_DMA_MASK_BITS);