diff mbox series

net/sfc: fix speed capabilities reported in device info

Message ID 1553013360-12880-1-git-send-email-arybchenko@solarflare.com (mailing list archive)
State Accepted, archived
Delegated to: Ferruh Yigit
Headers
Series net/sfc: fix speed capabilities reported in device info |

Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/intel-Performance-Testing success Performance Testing PASS
ci/mellanox-Performance-Testing success Performance Testing PASS
ci/checkpatch success coding style OK

Commit Message

Andrew Rybchenko March 19, 2019, 4:36 p.m. UTC 
  Phy capabilities are bit offsets in libefx, but was used as bit masks.

Fixes: d23f3a89ab54 ("net/sfc: support link speed and duplex settings")
Fixes: f82e33afbbb9 ("net/sfc: support link speeds up to 100G")
Cc: stable@dpdk.org

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
 drivers/net/sfc/sfc_ethdev.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Ferruh Yigit March 21, 2019, 6:06 p.m. UTC | #1 
On 3/19/2019 4:36 PM, Andrew Rybchenko wrote:
> Phy capabilities are bit offsets in libefx, but was used as bit masks.
> 
> Fixes: d23f3a89ab54 ("net/sfc: support link speed and duplex settings")
> Fixes: f82e33afbbb9 ("net/sfc: support link speeds up to 100G")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>

Applied to dpdk-next-net/master, thanks.
diff mbox series

Patch

diff --git a/drivers/net/sfc/sfc_ethdev.c b/drivers/net/sfc/sfc_ethdev.c
index e7bfd8917..2675d4a8c 100644
--- a/drivers/net/sfc/sfc_ethdev.c
+++ b/drivers/net/sfc/sfc_ethdev.c
@@ -96,17 +96,17 @@  sfc_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 
 	/* Autonegotiation may be disabled */
 	dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
-	if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_1000FDX)
+	if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_1000FDX))
 		dev_info->speed_capa |= ETH_LINK_SPEED_1G;
-	if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_10000FDX)
+	if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_10000FDX))
 		dev_info->speed_capa |= ETH_LINK_SPEED_10G;
-	if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_25000FDX)
+	if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_25000FDX))
 		dev_info->speed_capa |= ETH_LINK_SPEED_25G;
-	if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_40000FDX)
+	if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_40000FDX))
 		dev_info->speed_capa |= ETH_LINK_SPEED_40G;
-	if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_50000FDX)
+	if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_50000FDX))
 		dev_info->speed_capa |= ETH_LINK_SPEED_50G;
-	if (sa->port.phy_adv_cap_mask & EFX_PHY_CAP_100000FDX)
+	if (sa->port.phy_adv_cap_mask & (1u << EFX_PHY_CAP_100000FDX))
 		dev_info->speed_capa |= ETH_LINK_SPEED_100G;
 
 	dev_info->max_rx_queues = sa->rxq_max;