diff mbox series

[v3] examples/l3fwd: fix unaligned memory access

Message ID 20190726132758.55217-1-hariprasad.govindharajan@intel.com (mailing list archive)
State Superseded, archived
Headers
Series [v3] examples/l3fwd: fix unaligned memory access |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Hariprasad Govindharajan July 26, 2019, 1:27 p.m. UTC 
  Fix unaligned memory access when reading IPv6 header which
leads to segmentation fault by changing aligned memory read
to unaligned memory read.

Bugzilla ID: 279
Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
Cc: maciej.czekaj@caviumnetworks.com
Cc: stable@dpdk.org
Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
---
V2: Added functions which will do unaligned load based on the
underlying architecture

V3: Removed functions added in V2 and replaced them with if macros
which will branch based on the underlying architecture. As per my
understanding since the unaligned load affects only Intel arch,
I added that function branch and left the original code for other arc.
Can someone with ARM and PowerPC arch, could you please validate this
patch and let me know?
---
 examples/l3fwd/l3fwd_em.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Comments

Anatoly Burakov July 26, 2019, 1:37 p.m. UTC | #1 
On 26-Jul-19 2:27 PM, hgovindh wrote:
> Fix unaligned memory access when reading IPv6 header which
> leads to segmentation fault by changing aligned memory read
> to unaligned memory read.
> 
> Bugzilla ID: 279
> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> Cc: maciej.czekaj@caviumnetworks.com
> Cc: stable@dpdk.org
> Signed-off-by: hgovindh <hariprasad.govindharajan@intel.com>
> ---
> V2: Added functions which will do unaligned load based on the
> underlying architecture
> 
> V3: Removed functions added in V2 and replaced them with if macros
> which will branch based on the underlying architecture. As per my
> understanding since the unaligned load affects only Intel arch,
> I added that function branch and left the original code for other arc.
> Can someone with ARM and PowerPC arch, could you please validate this
> patch and let me know?
> ---
>   examples/l3fwd/l3fwd_em.c | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
> index 5f499e005..ea9ca9491 100644
> --- a/examples/l3fwd/l3fwd_em.c
> +++ b/examples/l3fwd/l3fwd_em.c
> @@ -244,6 +244,7 @@ em_mask_key(void *key, xmm_t mask)
>   #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
>   #endif
>   
> +
>   static inline uint16_t

Unintended whitespace change?
diff mbox series

Patch

diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 5f499e005..ea9ca9491 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -244,6 +244,7 @@  em_mask_key(void *key, xmm_t mask)
 #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain
 #endif
 
+
 static inline uint16_t
 em_get_ipv4_dst_port(void *ipv4_hdr, uint16_t portid, void *lookup_struct)
 {
@@ -287,8 +288,11 @@  em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
 	 * Get part of 5 tuple: dst IP address lower 96 bits
 	 * and src IP address higher 32 bits.
 	 */
+#if defined RTE_ARCH_X86
+	key.xmm[1] = _mm_loadu_si128(data1);
+#else
 	key.xmm[1] = *(xmm_t *)data1;
-
+#endif
 	/*
 	 * Get part of 5 tuple: dst port and src port
 	 * and dst IP address higher 32 bits.