diff mbox series

[v5] Examples/l3fwd: fix unaligned memory access

Message ID 20190730132639.84137-1-hariprasad.govindharajan@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Thomas Monjalon
Headers
Series [v5] Examples/l3fwd: fix unaligned memory access |

Checks

Context Check Description
ci/iol-Compile-Testing success Compile Testing PASS
ci/Intel-compilation success Compilation OK
ci/mellanox-Performance-Testing success Performance Testing PASS
ci/checkpatch success coding style OK

Commit Message

Hariprasad Govindharajan July 30, 2019, 1:26 p.m. UTC 
  Fix unaligned memory access when reading IPv6 header which
leads to segmentation fault by changing aligned memory read
to unaligned memory read.

Bugzilla ID: 279
Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
Cc: maciej.czekaj@caviumnetworks.com
Cc: stable@dpdk.org
Signed-off-by: Hariprasad Govindharajan <hariprasad.govindharajan@intel.com>
Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
V2: Added functions which will do unaligned load based on the
underlying architecture

V3: Removed functions added in V2 and replaced them with if macros
which will branch based on the underlying architecture. As per my
understanding since the unaligned load affects only Intel arch,
I added that function branch and left the original code for other arc.
Can someone with ARM and PowerPC arch, could you please validate this
patch and let me know?

V5: Fixed coding style issues.
---
 examples/l3fwd/l3fwd_em.c | 4 ++++
 1 file changed, 4 insertions(+)

Comments

Herakliusz Lipiec July 30, 2019, 3:48 p.m. UTC | #1 
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Hariprasad
> Govindharajan
> 
> Fix unaligned memory access when reading IPv6 header which leads to
> segmentation fault by changing aligned memory read to unaligned memory
> read.
> 
> Bugzilla ID: 279
> Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> Cc: maciej.czekaj@caviumnetworks.com
> Cc: stable@dpdk.org
> Signed-off-by: Hariprasad Govindharajan
> <hariprasad.govindharajan@intel.com>
> Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
> Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> ---

Tested-by: Herakliusz Lipiec <herakliusz.lipiec@intel.com>
Reviewed-by: Herakliusz Lipiec <herakliusz.lipiec@intel.com>
Thomas Monjalon July 30, 2019, 7:58 p.m. UTC | #2 
30/07/2019 17:48, Lipiec, Herakliusz:
> > From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Hariprasad
> > Govindharajan
> > 
> > Fix unaligned memory access when reading IPv6 header which leads to
> > segmentation fault by changing aligned memory read to unaligned memory
> > read.
> > 
> > Bugzilla ID: 279
> > Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build")
> > Cc: maciej.czekaj@caviumnetworks.com
> > Cc: stable@dpdk.org
> > Signed-off-by: Hariprasad Govindharajan
> > <hariprasad.govindharajan@intel.com>
> > Reviewed-by: Bruce Richardson <bruce.richardson@intel.com>
> > Reviewed-by: Jerin Jacob <jerinj@marvell.com>
> 
> Tested-by: Herakliusz Lipiec <herakliusz.lipiec@intel.com>
> Reviewed-by: Herakliusz Lipiec <herakliusz.lipiec@intel.com>

Applied, thanks
diff mbox series

Patch

diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c
index 5f499e005..74a7c8fa4 100644
--- a/examples/l3fwd/l3fwd_em.c
+++ b/examples/l3fwd/l3fwd_em.c
@@ -287,7 +287,11 @@  em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct)
 	 * Get part of 5 tuple: dst IP address lower 96 bits
 	 * and src IP address higher 32 bits.
 	 */
+#if defined RTE_ARCH_X86
+	key.xmm[1] = _mm_loadu_si128(data1);
+#else
 	key.xmm[1] = *(xmm_t *)data1;
+#endif
 
 	/*
 	 * Get part of 5 tuple: dst port and src port