diff mbox series

net/e1000: fix unchecked return value coverity issue

Message ID 1564954020-38741-1-git-send-email-xiao.zhang@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Qi Zhang
Headers
Series net/e1000: fix unchecked return value coverity issue |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK
ci/iol-Compile-Testing success Compile Testing PASS
ci/intel-Performance-Testing success Performance Testing PASS
ci/mellanox-Performance-Testing success Performance Testing PASS

Commit Message

Xiao Zhang Aug. 4, 2019, 9:27 p.m. UTC 
  Add return value checking when reading configure information from PCI
register to avoid coverity issue.

Fixes: 1fc97012 ("net/e1000: fix i219 hang on reset/close")
Cc: stable@dpdk.org

Signed-off-by: Xiao Zhang <xiao.zhang@intel.com>
---
 drivers/net/e1000/em_rxtx.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

Comments

Xiaolong Ye Aug. 5, 2019, 5:39 a.m. UTC | #1 
On 08/05, Xiao Zhang wrote:
>Add return value checking when reading configure information from PCI
>register to avoid coverity issue.
>
>Fixes: 1fc97012 ("net/e1000: fix i219 hang on reset/close")
>Cc: stable@dpdk.org
>
>Signed-off-by: Xiao Zhang <xiao.zhang@intel.com>
>---
> drivers/net/e1000/em_rxtx.c | 18 +++++++++++++++---
> 1 file changed, 15 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/net/e1000/em_rxtx.c b/drivers/net/e1000/em_rxtx.c
>index 6f40b45..5925e49 100644
>--- a/drivers/net/e1000/em_rxtx.c
>+++ b/drivers/net/e1000/em_rxtx.c
>@@ -2109,20 +2109,32 @@ em_flush_desc_rings(struct rte_eth_dev *dev)
> 	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
> 	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
> 	uint16_t pci_cfg_status = 0;
>+	int ret;
> 
> 	fextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
> 	E1000_WRITE_REG(hw, E1000_FEXTNVM11,
> 			fextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);
> 	tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
>-	rte_pci_read_config(pci_dev, &pci_cfg_status, sizeof(pci_cfg_status),
>-				PCI_CFG_STATUS_REG);
>+	ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
>+		   sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
>+	if (ret < 0) {
>+		PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
>+			    PCI_CFG_STATUS_REG);
>+		return;
>+	}
> 
> 	/* do nothing if we're not in faulty state, or if the queue is empty */
> 	if ((pci_cfg_status & FLUSH_DESC_REQUIRED) && tdlen) {
> 		/* flush desc ring */
> 		e1000_flush_tx_ring(dev);
>-		rte_pci_read_config(pci_dev, &pci_cfg_status,
>+		ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
> 				sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
>+		if (ret < 0) {
>+			PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
>+					PCI_CFG_STATUS_REG);
>+			return;
>+		}
>+
> 		if (pci_cfg_status & FLUSH_DESC_REQUIRED)
> 			e1000_flush_rx_ring(dev);
> 	}
>-- 
>2.7.4
>

Reviewed-by: Xiaolong Ye <xiaolong.ye@intel.com>
Qi Zhang Aug. 6, 2019, 11:14 a.m. UTC | #2 
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Ye Xiaolong
> Sent: Monday, August 5, 2019 1:39 PM
> To: Zhang, Xiao <xiao.zhang@intel.com>
> Cc: dev@dpdk.org; Lu, Wenzhuo <wenzhuo.lu@intel.com>; stable@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH] net/e1000: fix unchecked return value
> coverity issue
> 
> On 08/05, Xiao Zhang wrote:
> >Add return value checking when reading configure information from PCI
> >register to avoid coverity issue.
> >
> >Fixes: 1fc97012 ("net/e1000: fix i219 hang on reset/close")
> >Cc: stable@dpdk.org
> >
> >Signed-off-by: Xiao Zhang <xiao.zhang@intel.com>
> >
> Reviewed-by: Xiaolong Ye <xiaolong.ye@intel.com>

Applied to dpdk-next-net-intel.

Thanks
Qi
diff mbox series

Patch

diff --git a/drivers/net/e1000/em_rxtx.c b/drivers/net/e1000/em_rxtx.c
index 6f40b45..5925e49 100644
--- a/drivers/net/e1000/em_rxtx.c
+++ b/drivers/net/e1000/em_rxtx.c
@@ -2109,20 +2109,32 @@  em_flush_desc_rings(struct rte_eth_dev *dev)
 	struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 	struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 	uint16_t pci_cfg_status = 0;
+	int ret;
 
 	fextnvm11 = E1000_READ_REG(hw, E1000_FEXTNVM11);
 	E1000_WRITE_REG(hw, E1000_FEXTNVM11,
 			fextnvm11 | E1000_FEXTNVM11_DISABLE_MULR_FIX);
 	tdlen = E1000_READ_REG(hw, E1000_TDLEN(0));
-	rte_pci_read_config(pci_dev, &pci_cfg_status, sizeof(pci_cfg_status),
-				PCI_CFG_STATUS_REG);
+	ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
+		   sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
+	if (ret < 0) {
+		PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
+			    PCI_CFG_STATUS_REG);
+		return;
+	}
 
 	/* do nothing if we're not in faulty state, or if the queue is empty */
 	if ((pci_cfg_status & FLUSH_DESC_REQUIRED) && tdlen) {
 		/* flush desc ring */
 		e1000_flush_tx_ring(dev);
-		rte_pci_read_config(pci_dev, &pci_cfg_status,
+		ret = rte_pci_read_config(pci_dev, &pci_cfg_status,
 				sizeof(pci_cfg_status), PCI_CFG_STATUS_REG);
+		if (ret < 0) {
+			PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
+					PCI_CFG_STATUS_REG);
+			return;
+		}
+
 		if (pci_cfg_status & FLUSH_DESC_REQUIRED)
 			e1000_flush_rx_ring(dev);
 	}