[1/2] net/mlx5: fix Rx CQ doorbell synchronization on aarch64
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Commit Message
The Rx completion queue doorbell field needs to be updated after
the last CQE decompressed. For the weaker memory model processors,
the compiler barrier is not sufficient to guarantee the order of
these operations, so use the coherent I/O memory barrier to make
sure these fields are updated in order.
Fixes: 570acdb1da8a ("net/mlx5: add vectorized Rx/Tx burst for ARM")
Cc: stable@dpdk.org
Suggested-by: Gavin Hu <gavin.hu@arm.com>
Signed-off-by: Phil Yang <phil.yang@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
---
drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Comments
From: Phil Yang
> Subject: [PATCH 1/2] net/mlx5: fix Rx CQ doorbell synchronization on aarch64
>
> The Rx completion queue doorbell field needs to be updated after the last
> CQE decompressed. For the weaker memory model processors, the compiler
> barrier is not sufficient to guarantee the order of these operations, so use
> the coherent I/O memory barrier to make sure these fields are updated in
> order.
>
> Fixes: 570acdb1da8a ("net/mlx5: add vectorized Rx/Tx burst for ARM")
> Cc: stable@dpdk.org
>
> Suggested-by: Gavin Hu <gavin.hu@arm.com>
> Signed-off-by: Phil Yang <phil.yang@arm.com>
> Reviewed-by: Gavin Hu <gavin.hu@arm.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Hi,
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Phil Yang
> Sent: Thursday, September 5, 2019 1:55 PM
> To: Yongseok Koh <yskoh@mellanox.com>; Slava Ovsiienko
> <viacheslavo@mellanox.com>; Matan Azrad <matan@mellanox.com>; Nélio
> Laranjeiro <nelio.laranjeiro@6wind.com>; dev@dpdk.org
> Cc: Thomas Monjalon <thomas@monjalon.net>; jerinj@marvell.com;
> Honnappa.Nagarahalli@arm.com; gavin.hu@arm.com; nd@arm.com;
> stable@dpdk.org
> Subject: [dpdk-dev] [PATCH 1/2] net/mlx5: fix Rx CQ doorbell
> synchronization on aarch64
>
> The Rx completion queue doorbell field needs to be updated after
> the last CQE decompressed. For the weaker memory model processors,
> the compiler barrier is not sufficient to guarantee the order of
> these operations, so use the coherent I/O memory barrier to make
> sure these fields are updated in order.
>
> Fixes: 570acdb1da8a ("net/mlx5: add vectorized Rx/Tx burst for ARM")
> Cc: stable@dpdk.org
>
> Suggested-by: Gavin Hu <gavin.hu@arm.com>
> Signed-off-by: Phil Yang <phil.yang@arm.com>
> Reviewed-by: Gavin Hu <gavin.hu@arm.com>
> ---
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
@@ -727,7 +727,7 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts, uint16_t pkts_n,
rxq->decompressed -= n;
}
}
- rte_compiler_barrier();
+ rte_cio_wmb();
*rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
return rcvd_pkt;
}