diff mbox series

[v2,14/16] vhost: cache address translation result

Message ID	20190919163643.24130-15-yong.liu@intel.com (mailing list archive)
State	Superseded, archived
Headers	From: Marvin Liu <yong.liu@intel.com> To: maxime.coquelin@redhat.com, tiwei.bie@intel.com, zhihong.wang@intel.com Cc: dev@dpdk.org, Marvin Liu <yong.liu@intel.com> Date: Fri, 20 Sep 2019 00:36:41 +0800 Message-Id: <20190919163643.24130-15-yong.liu@intel.com> In-Reply-To: <20190919163643.24130-1-yong.liu@intel.com> References: <20190905161421.55981-2-yong.liu@intel.com> <20190919163643.24130-1-yong.liu@intel.com> Subject: [dpdk-dev] [PATCH v2 14/16] vhost: cache address translation result Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	vhost packed ring performance optimization \| [v2,00/16] vhost packed ring performance optimization [v2,01/16] vhost: add single packet enqueue function [v2,02/16] vhost: unify unroll pragma parameter [v2,03/16] vhost: add burst enqueue function for packed ring [v2,04/16] vhost: add single packet dequeue function [v2,05/16] vhost: add burst dequeue function [v2,06/16] vhost: rename flush shadow used ring functions [v2,07/16] vhost: flush vhost enqueue shadow ring by burst [v2,08/16] vhost: add flush function for burst enqueue [v2,09/16] vhost: buffer vhost dequeue shadow ring [v2,10/16] vhost: split enqueue and dequeue flush functions [v2,11/16] vhost: optimize enqueue function of packed ring [v2,12/16] vhost: add burst and single zero dequeue functions [v2,13/16] vhost: optimize dequeue function of packed ring [v2,14/16] vhost: cache address translation result [v2,15/16] vhost: check whether disable software pre-fetch [v2,16/16] vhost: optimize packed ring dequeue when in-order

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK
ci/Intel-compilation	fail	Compilation issues

Commit Message

Marvin Liu Sept. 19, 2019, 4:36 p.m. UTC

  Cache address translation result and use it in next translation. Due
to limited regions are supported, buffers are most likely in same
region when doing data transmission.

Signed-off-by: Marvin Liu <yong.liu@intel.com>

diff mbox series

Patch

diff --git a/lib/librte_vhost/rte_vhost.h b/lib/librte_vhost/rte_vhost.h
index 7fb172912..d90235cd6 100644
--- a/lib/librte_vhost/rte_vhost.h
+++ b/lib/librte_vhost/rte_vhost.h
@@ -91,10 +91,18 @@  struct rte_vhost_mem_region {
 	int fd;
 };
 
+struct rte_vhost_mem_region_cache {
+	uint64_t guest_phys_addr;
+	uint64_t guest_phys_addr_end;
+	int64_t host_user_addr_offset;
+	uint64_t size;
+};
+
 /**
  * Memory structure includes region and mapping information.
  */
 struct rte_vhost_memory {
+	struct rte_vhost_mem_region_cache cache_region;
 	uint32_t nregions;
 	struct rte_vhost_mem_region regions[];
 };
@@ -232,11 +240,30 @@  rte_vhost_va_from_guest_pa(struct rte_vhost_memory *mem,
 	struct rte_vhost_mem_region *r;
 	uint32_t i;
 
+	struct rte_vhost_mem_region_cache *r_cache;
+	/* check with cached region */
+	r_cache = &mem->cache_region;
+	if (likely(gpa >= r_cache->guest_phys_addr && gpa <
+		   r_cache->guest_phys_addr_end)) {
+		if (unlikely(*len > r_cache->guest_phys_addr_end - gpa))
+			*len = r_cache->guest_phys_addr_end - gpa;
+
+		return gpa - r_cache->host_user_addr_offset;
+	}
+
+
 	for (i = 0; i < mem->nregions; i++) {
 		r = &mem->regions[i];
 		if (gpa >= r->guest_phys_addr &&
 		    gpa <  r->guest_phys_addr + r->size) {
 
+			r_cache->guest_phys_addr = r->guest_phys_addr;
+			r_cache->guest_phys_addr_end = r->guest_phys_addr +
+						       r->size;
+			r_cache->size = r->size;
+			r_cache->host_user_addr_offset = r->guest_phys_addr -
+							 r->host_user_addr;
+
 			if (unlikely(*len > r->guest_phys_addr + r->size - gpa))
 				*len = r->guest_phys_addr + r->size - gpa;