diff mbox series

[v2,10/20] crypto/dpaa2_sec: disable 'write-safe' for PDCP

Message ID 20190930115237.5073-11-akhil.goyal@nxp.com (mailing list archive)
State Superseded, archived
Delegated to: akhil goyal
Headers
Series crypto/dpaaX_sec: Support Wireless algos |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail Compilation issues

Commit Message

Akhil Goyal Sept. 30, 2019, 11:52 a.m. UTC 
  From: Vakul Garg <vakul.garg@nxp.com>

PDCP descriptors in some cases internally use commands which overwrite
memory with extra '0s' if write-safe is kept enabled. This breaks
correct functional behavior of PDCP apis and they in many cases give
incorrect crypto output. There we disable 'write-safe' bit in FLC for
PDCP cases. If there is a performance drop, then write-safe would be
enabled selectively through a separate patch.

Signed-off-by: Vakul Garg <vakul.garg@nxp.com>
Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
---
 drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 36ae78a03..d53720ae3 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -2931,8 +2931,12 @@  dpaa2_sec_set_pdcp_session(struct rte_cryptodev *dev,
 
 	flc->word1_sdl = (uint8_t)bufsize;
 
-	/* Set EWS bit i.e. enable write-safe */
-	DPAA2_SET_FLC_EWS(flc);
+	/* TODO - check the perf impact or
+	 * align as per descriptor type
+	 * Set EWS bit i.e. enable write-safe
+	 * DPAA2_SET_FLC_EWS(flc);
+	 */
+
 	/* Set BS = 1 i.e reuse input buffers as output buffers */
 	DPAA2_SET_FLC_REUSE_BS(flc);
 	/* Set FF = 10; reuse input buffers if they provide sufficient space */