net/octeontx2: add check for PTP and HIGIG2
Checks
Commit Message
From: Kiran Kumar K <kirankumark@marvell.com>
For octeontx2 we won't support both PTP and HIGIG2 together.
Added a check to verify this.
Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
drivers/net/octeontx2/otx2_ethdev.c | 9 ++++++++-
drivers/net/octeontx2/otx2_ptp.c | 5 +++++
2 files changed, 13 insertions(+), 1 deletion(-)
Comments
On Mon, Jan 13, 2020 at 9:55 AM <kirankumark@marvell.com> wrote:
>
> From: Kiran Kumar K <kirankumark@marvell.com>
>
> For octeontx2 we won't support both PTP and HIGIG2 together.
> Added a check to verify this.
Since it is a bug fix, Could change to the following or similar and send v2:
net/octeontx2: fix PTP and HIGIG2 coexistence.
octeontx2 PMD does not support both PTP and HIGIG2 together.
added a check to enforce this and updated the Rx offload capabilities when
Higig2 mode enabled.
Fixes: ..
Cc: stable@dpdk.org
>
> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
> ---
> drivers/net/octeontx2/otx2_ethdev.c | 9 ++++++++-
> drivers/net/octeontx2/otx2_ptp.c | 5 +++++
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
> index ed329273d..b4c68191d 100644
> --- a/drivers/net/octeontx2/otx2_ethdev.c
> +++ b/drivers/net/octeontx2/otx2_ethdev.c
> @@ -18,7 +18,8 @@ nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
> {
> uint64_t capa = NIX_RX_OFFLOAD_CAPA;
>
> - if (otx2_dev_is_vf(dev))
> + if (otx2_dev_is_vf(dev) ||
> + dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
> capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
>
> return capa;
> @@ -1641,6 +1642,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
> goto fail_offloads;
> }
>
> + if (dev->ptp_en &&
> + dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
> + otx2_err(" Both PTP and switch header enabled");
Please remove the space before "Both.."
I think, we can use the below error message also here.
> + goto free_nix_lf;
> + }
> +
> rc = nix_lf_switch_header_type_enable(dev);
> if (rc) {
> otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
> diff --git a/drivers/net/octeontx2/otx2_ptp.c b/drivers/net/octeontx2/otx2_ptp.c
> index f34b9339c..74cb007a0 100644
> --- a/drivers/net/octeontx2/otx2_ptp.c
> +++ b/drivers/net/octeontx2/otx2_ptp.c
> @@ -221,6 +221,11 @@ otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)
> return -EINVAL;
> }
>
> + if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
> + otx2_err("PTP mode not supported in HIGIG mode");
See above.
> + return -EINVAL;
> + }
> +
> /* Allocating a iova address for tx tstamp */
> const struct rte_memzone *ts;
> ts = rte_eth_dma_zone_reserve(eth_dev, "otx2_ts",
> --
> 2.17.1
>
@@ -18,7 +18,8 @@ nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
{
uint64_t capa = NIX_RX_OFFLOAD_CAPA;
- if (otx2_dev_is_vf(dev))
+ if (otx2_dev_is_vf(dev) ||
+ dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
return capa;
@@ -1641,6 +1642,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
goto fail_offloads;
}
+ if (dev->ptp_en &&
+ dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+ otx2_err(" Both PTP and switch header enabled");
+ goto free_nix_lf;
+ }
+
rc = nix_lf_switch_header_type_enable(dev);
if (rc) {
otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
@@ -221,6 +221,11 @@ otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)
return -EINVAL;
}
+ if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+ otx2_err("PTP mode not supported in HIGIG mode");
+ return -EINVAL;
+ }
+
/* Allocating a iova address for tx tstamp */
const struct rte_memzone *ts;
ts = rte_eth_dma_zone_reserve(eth_dev, "otx2_ts",