[v4] eal/arm64: fix rdtsc precise version
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Commit Message
In order to get more accurate the cntvct_el0 reading,
SW must invoke isb and arch_counter_enforce_ordering.
Reference of linux kernel:
https://git.kernel.org/pub/scm/linux/kernel/git/
torvalds/linux.git/tree/arch/arm64/include/asm/arch_timer.h?h=v5.5#n220
Fixes: ccad39ea0712 ("eal/arm: add cpu cycle operations for ARMv8")
Cc: stable@dpdk.org
Signed-off-by: Haifeng Lin <haifeng.lin@huawei.com>
---
.../common/include/arch/arm/rte_atomic_64.h | 3 +++
.../common/include/arch/arm/rte_cycles_64.h | 20 +++++++++++++++++--
2 files changed, 21 insertions(+), 2 deletions(-)
@@ -21,6 +21,7 @@ extern "C" {
#define dsb(opt) asm volatile("dsb " #opt : : : "memory")
#define dmb(opt) asm volatile("dmb " #opt : : : "memory")
+#define isb() (asm volatile("isb" : : : "memory"))
#define rte_mb() dsb(sy)
@@ -44,6 +45,8 @@ extern "C" {
#define rte_cio_rmb() dmb(oshld)
+#define rte_isb() isb()
+
/*------------------------ 128 bit atomic operations -------------------------*/
#if defined(__ARM_FEATURE_ATOMICS) || defined(RTE_ARM_FEATURE_ATOMICS)
@@ -18,6 +18,7 @@ extern "C" {
* The time base for this lcore.
*/
#ifndef RTE_ARM_EAL_RDTSC_USE_PMU
+
/**
* This call is portable to any ARMv8 architecture, however, typically
* cntvct_el0 runs at <= 100MHz and it may be imprecise for some tasks.
@@ -59,11 +60,26 @@ rte_rdtsc(void)
}
#endif
+#define arch_counter_enforce_ordering(val) do { \
+ uint64_t tmp, _val = (val); \
+ \
+ asm volatile( \
+ " eor %0, %1, %1\n" \
+ " add %0, sp, %0\n" \
+ " ldr xzr, [%0]" \
+ : "=r" (tmp) : "r" (_val)); \
+} while (0)
+
+
static inline uint64_t
rte_rdtsc_precise(void)
{
- rte_mb();
- return rte_rdtsc();
+ uint64_t tsc;
+
+ rte_isb();
+ tsc = rte_rdtsc();
+ arch_counter_enforce_ordering(tsc);
+ return tsc;
}
static inline uint64_t