diff mbox series

[5/6] net/qede: add VF FLR support

Message ID 20200609194207.24328-6-manishc@marvell.com (mailing list archive)
State Changes Requested, archived
Delegated to: Jerin Jacob
Headers
Series qede: SR-IOV PF driver support |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Manish Chopra June 9, 2020, 7:42 p.m. UTC 
  This patch adds required bit to handle VF FLR
indication from Management FW (MFW) of the device

With that VFs were able to load in VM (VF attached as PCI
passthrough to the guest VM) followed by FLR successfully.

Signed-off-by: Manish Chopra <manishc@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Rasesh Mody <rmody@marvell.com>
---
 drivers/net/qede/base/bcm_osal.c |  5 +++++
 drivers/net/qede/base/bcm_osal.h |  4 +++-
 drivers/net/qede/qede_sriov.c    | 18 ++++++++++++++++++
 3 files changed, 26 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c
index 1f6466a32..78524431c 100644
--- a/drivers/net/qede/base/bcm_osal.c
+++ b/drivers/net/qede/base/bcm_osal.c
@@ -33,6 +33,11 @@  int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn)
 	return rc;
 }
 
+void osal_vf_flr_update(struct ecore_hwfn *p_hwfn)
+{
+	qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
+}
+
 void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie)
 {
 	struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie;
diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h
index b55802952..cb3711210 100644
--- a/drivers/net/qede/base/bcm_osal.h
+++ b/drivers/net/qede/base/bcm_osal.h
@@ -352,7 +352,9 @@  u32 qede_find_first_zero_bit(unsigned long *, u32);
 /* SR-IOV channel */
 
 int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn);
-#define OSAL_VF_FLR_UPDATE(hwfn) nothing
+void osal_vf_flr_update(struct ecore_hwfn *p_hwfn);
+#define OSAL_VF_FLR_UPDATE(hwfn) \
+	osal_vf_flr_update(hwfn)
 #define OSAL_VF_SEND_MSG2PF(dev, done, msg, reply_addr, msg_size, reply_size) 0
 #define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol)	(0)
 #define OSAL_PF_VF_MSG(hwfn, vfid) \
diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c
index 125e5058b..a486b0496 100644
--- a/drivers/net/qede/qede_sriov.c
+++ b/drivers/net/qede/qede_sriov.c
@@ -151,6 +151,7 @@  static void qed_handle_bulletin_post(struct ecore_hwfn *hwfn)
 void qed_iov_pf_task(void *arg)
 {
 	struct ecore_hwfn *p_hwfn = arg;
+	int rc;
 
 	if (qede_test_bit(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags)) {
 		qede_clr_bit(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags);
@@ -163,6 +164,23 @@  void qed_iov_pf_task(void *arg)
 			     &p_hwfn->iov_task_flags);
 		qed_handle_bulletin_post(p_hwfn);
 	}
+
+	if (qede_test_bit(QED_IOV_WQ_FLR_FLAG, &p_hwfn->iov_task_flags)) {
+		struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn);
+
+		qede_clr_bit(QED_IOV_WQ_FLR_FLAG, &p_hwfn->iov_task_flags);
+
+		if (!p_ptt) {
+			qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
+			return;
+		}
+
+		rc = ecore_iov_vf_flr_cleanup(p_hwfn, p_ptt);
+		if (rc)
+			qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
+
+		ecore_ptt_release(p_hwfn, p_ptt);
+	}
 }
 
 int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag)