Add mlx5 PCI bus which enables multiple mlx5 drivers to bind to single
pci device.
Signed-off-by: Parav Pandit <parav@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
---
Changelog:
v4->v5:
- Merged maintainers update patch with this patch
v2->v3:
- Addressed comments from Thomas and Asaf
- Moved pci_driver structure instance as first in driver
- Removed white spaces at the end of line in diagram
- Address comments from Matan
- Removed CONFIG_RTE_LIBRTE_MLX5_PCI_BUS from config files
- Changed alignedment to mlx5 specific aligment instead of standard
DPDK
- Using uint32_t instead of mlx5_class enum
v1->v2:
- Address comments from Thomas and Gaetan
- Inheriting ret_pci_driver instead of rte_driver
- Added design and description of the mlx5_pci bus
---
MAINTAINERS | 5 ++
drivers/bus/meson.build | 2 +-
drivers/bus/mlx5_pci/Makefile | 38 +++++++++
drivers/bus/mlx5_pci/meson.build | 19 +++++
drivers/bus/mlx5_pci/mlx5_pci_bus.c | 14 ++++
drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h | 84 +++++++++++++++++++
.../bus/mlx5_pci/rte_bus_mlx5_pci_version.map | 5 ++
7 files changed, 166 insertions(+), 1 deletion(-)
create mode 100644 drivers/bus/mlx5_pci/Makefile
create mode 100644 drivers/bus/mlx5_pci/meson.build
create mode 100644 drivers/bus/mlx5_pci/mlx5_pci_bus.c
create mode 100644 drivers/bus/mlx5_pci/rte_bus_mlx5_pci.h
create mode 100644 drivers/bus/mlx5_pci/rte_bus_mlx5_pci_version.map
@@ -517,6 +517,11 @@ Intel FPGA bus
M: Rosen Xu <rosen.xu@intel.com>
F: drivers/bus/ifpga/
+Melllanox mlx5 PCI bus driver
+M: Parav Pandit <parav@mellaox.com>
+M: Matan Azrad <matan@mellanox.com>
+F: drivers/bus/mlx5_pci
+
NXP buses
M: Hemant Agrawal <hemant.agrawal@nxp.com>
M: Sachin Saxena <sachin.saxena@nxp.com>
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2017 Intel Corporation
-drivers = ['dpaa', 'fslmc', 'ifpga', 'pci', 'vdev', 'vmbus']
+drivers = ['dpaa', 'fslmc', 'ifpga', 'pci', 'mlx5_pci', 'vdev', 'vmbus']
std_deps = ['eal']
config_flag_fmt = 'RTE_LIBRTE_@0@_BUS'
driver_name_fmt = 'rte_bus_@0@'
new file mode 100644
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright 2020 Mellanox Technologies, Ltd
+
+include $(RTE_SDK)/mk/rte.vars.mk
+
+#
+# library name
+#
+LIB = librte_bus_mlx5_pci.a
+
+CFLAGS += -O3 -Wall -Wextra
+CFLAGS += $(WERROR_FLAGS)
+CFLAGS += -Wno-strict-prototypes
+CFLAGS += -I$(RTE_SDK)/drivers/common/mlx5
+CFLAGS += -I$(BUILDDIR)/drivers/common/mlx5
+CFLAGS += -I$(RTE_SDK)/drivers/common/mlx5/linux
+CFLAGS += -I$(RTE_SDK)/drivers/bus/pci
+LDLIBS += -lrte_eal
+LDLIBS += -lrte_common_mlx5
+LDLIBS += -lrte_pci -lrte_bus_pci
+
+# versioning export map
+EXPORT_MAP := rte_bus_mlx5_pci_version.map
+
+SRCS-y += mlx5_pci_bus.c
+
+# DEBUG which is usually provided on the command-line may enable
+# CONFIG_RTE_LIBRTE_MLX5_DEBUG.
+ifeq ($(DEBUG),1)
+CONFIG_RTE_LIBRTE_MLX5_DEBUG := y
+endif
+
+#
+# Export include files
+#
+SYMLINK-y-include += rte_bus_mlx5_pci.h
+
+include $(RTE_SDK)/mk/rte.lib.mk
new file mode 100644
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(c) 2020 Mellanox Technologies Ltd
+
+deps += ['pci', 'bus_pci', 'common_mlx5']
+install_headers('rte_bus_mlx5_pci.h')
+sources = files('mlx5_pci_bus.c')
+
+cflags_options = [
+ '-std=c11',
+ '-Wno-strict-prototypes',
+ '-D_BSD_SOURCE',
+ '-D_DEFAULT_SOURCE',
+ '-D_XOPEN_SOURCE=600'
+]
+foreach option:cflags_options
+ if cc.has_argument(option)
+ cflags += option
+ endif
+endforeach
new file mode 100644
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2020 Mellanox Technologies, Ltd
+ */
+
+#include "rte_bus_mlx5_pci.h"
+
+static TAILQ_HEAD(mlx5_pci_bus_drv_head, rte_mlx5_pci_driver) drv_list =
+ TAILQ_HEAD_INITIALIZER(drv_list);
+
+void
+rte_mlx5_pci_driver_register(struct rte_mlx5_pci_driver *driver)
+{
+ TAILQ_INSERT_TAIL(&drv_list, driver, next);
+}
new file mode 100644
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2020 Mellanox Technologies, Ltd
+ */
+
+#ifndef _RTE_BUS_MLX5_PCI_H_
+#define _RTE_BUS_MLX5_PCI_H_
+
+/**
+ * @file
+ *
+ * RTE Mellanox PCI Bus Interface
+ * Mellanox ConnectX PCI device supports multiple class (net/vdpa/regex)
+ * devices. This bus enables creating such multiple class of devices on a
+ * single PCI device by allowing to bind multiple class specific device
+ * driver to attach to mlx5_pci bus driver.
+ *
+ * ----------- ------------ -----------------
+ * | mlx5 | | mlx5 | | mlx5 |
+ * | net pmd | | vdpa pmd | | new class pmd |
+ * ----------- ------------ -----------------
+ * \ | /
+ * \ | /
+ * \ ------------- /
+ * \______| mlx5 |_____ /
+ * | pci bus |
+ * -------------
+ * |
+ * -----------
+ * | mlx5 |
+ * | pci dev |
+ * -----------
+ *
+ * - mlx5 pci bus driver binds to mlx5 PCI devices defined by PCI
+ * ID table of all related mlx5 PCI devices.
+ * - mlx5 class driver such as net, vdpa, regex PMD defines its
+ * specific PCI ID table and mlx5 bus driver probes matching
+ * class drivers.
+ * - mlx5 pci bus driver is cental place that validates supported
+ * class combinations.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#include <rte_pci.h>
+#include <rte_bus_pci.h>
+
+#include <mlx5_common.h>
+
+/**
+ * A structure describing a mlx5 pci driver.
+ */
+struct rte_mlx5_pci_driver {
+ struct rte_pci_driver pci_driver; /**< Inherit core pci driver. */
+ uint32_t dev_class; /**< Class of this driver, enum mlx5_class */
+ TAILQ_ENTRY(rte_mlx5_pci_driver) next;
+};
+
+/**
+ * Register a mlx5_pci device driver.
+ *
+ * @param driver
+ * A pointer to a rte_mlx5_pci_driver structure describing the driver
+ * to be registered.
+ */
+__rte_internal
+void
+rte_mlx5_pci_driver_register(struct rte_mlx5_pci_driver *driver);
+
+#define RTE_PMD_REGISTER_MLX5_PCI(nm, drv) \
+ static const char *mlx5_pci_drvinit_fn_ ## nm; \
+ RTE_INIT(mlx5_pci_drvinit_fn_ ##drv) \
+ { \
+ (drv).driver.name = RTE_STR(nm); \
+ rte_mlx5_pci_driver_register(&drv); \
+ } \
+ RTE_PMD_EXPORT_NAME(nm, __COUNTER__)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _RTE_BUS_MLX5_PCI_H_ */
new file mode 100644
@@ -0,0 +1,5 @@
+INTERNAL {
+ global:
+
+ rte_mlx5_pci_driver_register;
+};