[v8,4/4] net/ixgbe: use WC store to update queue tail registers
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Commit Message
Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
---
drivers/net/ixgbe/base/ixgbe_osdep.h | 6 ++++++
drivers/net/ixgbe/ixgbe_rxtx.c | 12 ++++++------
drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c | 4 ++--
3 files changed, 14 insertions(+), 8 deletions(-)
Comments
> Performance improvement: use a write combining store
> instead of a regular mmio write to update queue tail
> registers.
>
> Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
> ---
> drivers/net/ixgbe/base/ixgbe_osdep.h | 6 ++++++
> drivers/net/ixgbe/ixgbe_rxtx.c | 12 ++++++------
> drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c | 4 ++--
> 3 files changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/net/ixgbe/base/ixgbe_osdep.h b/drivers/net/ixgbe/base/ixgbe_osdep.h
> index dc712b7..cacf724 100644
> --- a/drivers/net/ixgbe/base/ixgbe_osdep.h
> +++ b/drivers/net/ixgbe/base/ixgbe_osdep.h
> @@ -105,6 +105,12 @@ static inline uint32_t ixgbe_read_addr(volatile void* addr)
> #define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
> rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
>
> +#define IXGBE_PCI_REG_WC_WRITE(reg, value) \
> + rte_write32_wc((rte_cpu_to_le_32(value)), reg)
> +
> +#define IXGBE_PCI_REG_WC_WRITE_RELAXED(reg, value) \
> + rte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg)
> +
> #define IXGBE_PCI_REG_ADDR(hw, reg) \
> ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
>
> diff --git a/drivers/net/ixgbe/ixgbe_rxtx.c b/drivers/net/ixgbe/ixgbe_rxtx.c
> index 2e20e18..669b23e 100644
> --- a/drivers/net/ixgbe/ixgbe_rxtx.c
> +++ b/drivers/net/ixgbe/ixgbe_rxtx.c
> @@ -308,7 +308,7 @@ tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
>
> /* update tail pointer */
> rte_wmb();
> - IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
> + IXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
>
> return nb_pkts;
> }
> @@ -946,7 +946,7 @@ ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
> PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
> (unsigned) txq->port_id, (unsigned) txq->queue_id,
> (unsigned) tx_id, (unsigned) nb_tx);
> - IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
> + IXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
> txq->tx_tail = tx_id;
>
> return nb_tx;
> @@ -1692,7 +1692,7 @@ rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
>
> /* update tail pointer */
> rte_wmb();
> - IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
> + IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr,
> cur_free_trigger);
> }
>
> @@ -1918,7 +1918,7 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
> (unsigned) nb_rx);
> rx_id = (uint16_t) ((rx_id == 0) ?
> (rxq->nb_rx_desc - 1) : (rx_id - 1));
> - IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
> + IXGBE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, rx_id);
> nb_hold = 0;
> }
> rxq->nb_rx_hold = nb_hold;
> @@ -2096,7 +2096,7 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
>
> if (!ixgbe_rx_alloc_bufs(rxq, false)) {
> rte_wmb();
> - IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
> + IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr,
> next_rdt);
> nb_hold -= rxq->rx_free_thresh;
> } else {
> @@ -2262,7 +2262,7 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
> rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
>
> rte_wmb();
> - IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
> + IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
> nb_hold = 0;
> }
>
> diff --git a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c
> index 517ca31..e77a7f3 100644
> --- a/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c
> +++ b/drivers/net/ixgbe/ixgbe_rxtx_vec_sse.c
> @@ -90,7 +90,7 @@ ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
> (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
>
> /* Update the tail pointer on the NIC */
> - IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
> + IXGBE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, rx_id);
> }
>
> #ifdef RTE_LIBRTE_SECURITY
> @@ -697,7 +697,7 @@ ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
>
> txq->tx_tail = tx_id;
>
> - IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
> + IXGBE_PCI_REG_WC_WRITE(txq->tdt_reg_addr, txq->tx_tail);
>
> return nb_pkts;
> }
> --
Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
> 2.7.4
@@ -105,6 +105,12 @@ static inline uint32_t ixgbe_read_addr(volatile void* addr)
#define IXGBE_PCI_REG_WRITE_RELAXED(reg, value) \
rte_write32_relaxed((rte_cpu_to_le_32(value)), reg)
+#define IXGBE_PCI_REG_WC_WRITE(reg, value) \
+ rte_write32_wc((rte_cpu_to_le_32(value)), reg)
+
+#define IXGBE_PCI_REG_WC_WRITE_RELAXED(reg, value) \
+ rte_write32_wc_relaxed((rte_cpu_to_le_32(value)), reg)
+
#define IXGBE_PCI_REG_ADDR(hw, reg) \
((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
@@ -308,7 +308,7 @@ tx_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
/* update tail pointer */
rte_wmb();
- IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
+ IXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, txq->tx_tail);
return nb_pkts;
}
@@ -946,7 +946,7 @@ ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
(unsigned) txq->port_id, (unsigned) txq->queue_id,
(unsigned) tx_id, (unsigned) nb_tx);
- IXGBE_PCI_REG_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
+ IXGBE_PCI_REG_WC_WRITE_RELAXED(txq->tdt_reg_addr, tx_id);
txq->tx_tail = tx_id;
return nb_tx;
@@ -1692,7 +1692,7 @@ rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
/* update tail pointer */
rte_wmb();
- IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
+ IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr,
cur_free_trigger);
}
@@ -1918,7 +1918,7 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
(unsigned) nb_rx);
rx_id = (uint16_t) ((rx_id == 0) ?
(rxq->nb_rx_desc - 1) : (rx_id - 1));
- IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
+ IXGBE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, rx_id);
nb_hold = 0;
}
rxq->nb_rx_hold = nb_hold;
@@ -2096,7 +2096,7 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
if (!ixgbe_rx_alloc_bufs(rxq, false)) {
rte_wmb();
- IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr,
+ IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr,
next_rdt);
nb_hold -= rxq->rx_free_thresh;
} else {
@@ -2262,7 +2262,7 @@ ixgbe_recv_pkts_lro(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts,
rxq->port_id, rxq->queue_id, rx_id, nb_hold, nb_rx);
rte_wmb();
- IXGBE_PCI_REG_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
+ IXGBE_PCI_REG_WC_WRITE_RELAXED(rxq->rdt_reg_addr, prev_id);
nb_hold = 0;
}
@@ -90,7 +90,7 @@ ixgbe_rxq_rearm(struct ixgbe_rx_queue *rxq)
(rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
/* Update the tail pointer on the NIC */
- IXGBE_PCI_REG_WRITE(rxq->rdt_reg_addr, rx_id);
+ IXGBE_PCI_REG_WC_WRITE(rxq->rdt_reg_addr, rx_id);
}
#ifdef RTE_LIBRTE_SECURITY
@@ -697,7 +697,7 @@ ixgbe_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
txq->tx_tail = tx_id;
- IXGBE_PCI_REG_WRITE(txq->tdt_reg_addr, txq->tx_tail);
+ IXGBE_PCI_REG_WC_WRITE(txq->tdt_reg_addr, txq->tx_tail);
return nb_pkts;
}