diff mbox series

[v3,02/18] eal: add default SIMD bitwidth values

Message ID 20200930130415.11211-3-ciara.power@intel.com (mailing list archive)
State Superseded, archived
Delegated to: David Marchand
Headers
Series add max SIMD bitwidth to EAL |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Power, Ciara Sept. 30, 2020, 1:03 p.m. UTC 
  Each arch has a define for the default SIMD bitwidth value, this is used
on EAL init to set the config max SIMD bitwidth.

Cc: Ruifeng Wang <ruifeng.wang@arm.com>
Cc: Jerin Jacob <jerinj@marvell.com>
Cc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Cc: David Christensen <drc@linux.vnet.ibm.com>

Signed-off-by: Ciara Power <ciara.power@intel.com>

---
v3:
  - Removed unnecessary define in generic rte_vect.h
  - Changed default bitwidth for ARM to UINT16_MAX, to allow for SVE.
v2: Changed default bitwidth for Arm to 128.
---
 lib/librte_eal/arm/include/rte_vect.h      | 2 ++
 lib/librte_eal/common/eal_common_options.c | 3 +++
 lib/librte_eal/ppc/include/rte_vect.h      | 2 ++
 lib/librte_eal/x86/include/rte_vect.h      | 2 ++
 4 files changed, 9 insertions(+)

Comments

David Christensen Oct. 5, 2020, 7:35 p.m. UTC | #1 
On 9/30/20 6:03 AM, Ciara Power wrote:
> Each arch has a define for the default SIMD bitwidth value, this is used
> on EAL init to set the config max SIMD bitwidth.
> 
> Cc: Ruifeng Wang <ruifeng.wang@arm.com>
> Cc: Jerin Jacob <jerinj@marvell.com>
> Cc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Cc: David Christensen <drc@linux.vnet.ibm.com>
> 
> Signed-off-by: Ciara Power <ciara.power@intel.com>
> 
> ---
> v3:
>    - Removed unnecessary define in generic rte_vect.h
>    - Changed default bitwidth for ARM to UINT16_MAX, to allow for SVE.
> v2: Changed default bitwidth for Arm to 128.
> ---
>   lib/librte_eal/arm/include/rte_vect.h      | 2 ++
>   lib/librte_eal/common/eal_common_options.c | 3 +++
>   lib/librte_eal/ppc/include/rte_vect.h      | 2 ++
>   lib/librte_eal/x86/include/rte_vect.h      | 2 ++
>   4 files changed, 9 insertions(+)
> 
Reviewed-By: David Christensen <drc@linux.vnet.ibm.com>
Ananyev, Konstantin Oct. 8, 2020, 1:17 p.m. UTC | #2 
> 
> Each arch has a define for the default SIMD bitwidth value, this is used
> on EAL init to set the config max SIMD bitwidth.
> 
> Cc: Ruifeng Wang <ruifeng.wang@arm.com>
> Cc: Jerin Jacob <jerinj@marvell.com>
> Cc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Cc: David Christensen <drc@linux.vnet.ibm.com>
> 
> Signed-off-by: Ciara Power <ciara.power@intel.com>
> 
> ---
> v3:
>   - Removed unnecessary define in generic rte_vect.h
>   - Changed default bitwidth for ARM to UINT16_MAX, to allow for SVE.
> v2: Changed default bitwidth for Arm to 128.
> ---
>  lib/librte_eal/arm/include/rte_vect.h      | 2 ++
>  lib/librte_eal/common/eal_common_options.c | 3 +++
>  lib/librte_eal/ppc/include/rte_vect.h      | 2 ++
>  lib/librte_eal/x86/include/rte_vect.h      | 2 ++
>  4 files changed, 9 insertions(+)
> 
> diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h
> index 01c51712a1..a3508e69d5 100644
> --- a/lib/librte_eal/arm/include/rte_vect.h
> +++ b/lib/librte_eal/arm/include/rte_vect.h
> @@ -14,6 +14,8 @@
>  extern "C" {
>  #endif
> 
> +#define RTE_DEFAULT_SIMD_BITWIDTH UINT16_MAX

As a nit - can we use here values from enum rte_max_simd_t?
That would make things more consistent...
Probably you'll need to move enum rte_max_simd_t definition
into rte_vect.h for that.

> +
>  typedef int32x4_t xmm_t;
> 
>  #define	XMM_SIZE	(sizeof(xmm_t))
> diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c
> index e9117a96af..d412cae89b 100644
> --- a/lib/librte_eal/common/eal_common_options.c
> +++ b/lib/librte_eal/common/eal_common_options.c
> @@ -35,6 +35,7 @@
>  #ifndef RTE_EXEC_ENV_WINDOWS
>  #include <rte_telemetry.h>
>  #endif
> +#include <rte_vect.h>
> 
>  #include "eal_internal_cfg.h"
>  #include "eal_options.h"
> @@ -344,6 +345,8 @@ eal_reset_internal_config(struct internal_config *internal_cfg)
>  	internal_cfg->user_mbuf_pool_ops_name = NULL;
>  	CPU_ZERO(&internal_cfg->ctrl_cpuset);
>  	internal_cfg->init_complete = 0;
> +	internal_cfg->max_simd_bitwidth.bitwidth = RTE_DEFAULT_SIMD_BITWIDTH;
> +	internal_cfg->max_simd_bitwidth.locked = 0;
>  }
> 
>  static int
> diff --git a/lib/librte_eal/ppc/include/rte_vect.h b/lib/librte_eal/ppc/include/rte_vect.h
> index b0545c878c..70fbd0c423 100644
> --- a/lib/librte_eal/ppc/include/rte_vect.h
> +++ b/lib/librte_eal/ppc/include/rte_vect.h
> @@ -15,6 +15,8 @@
>  extern "C" {
>  #endif
> 
> +#define RTE_DEFAULT_SIMD_BITWIDTH 256
> +
>  typedef vector signed int xmm_t;
> 
>  #define	XMM_SIZE	(sizeof(xmm_t))
> diff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/include/rte_vect.h
> index df5a607623..b1df75aca7 100644
> --- a/lib/librte_eal/x86/include/rte_vect.h
> +++ b/lib/librte_eal/x86/include/rte_vect.h
> @@ -35,6 +35,8 @@
>  extern "C" {
>  #endif
> 
> +#define RTE_DEFAULT_SIMD_BITWIDTH 256
> +
>  typedef __m128i xmm_t;
> 
>  #define	XMM_SIZE	(sizeof(xmm_t))
> --
> 2.17.1
David Marchand Oct. 8, 2020, 4:45 p.m. UTC | #3 
On Wed, Sep 30, 2020 at 3:09 PM Ciara Power <ciara.power@intel.com> wrote:
>
> Each arch has a define for the default SIMD bitwidth value, this is used
> on EAL init to set the config max SIMD bitwidth.
>
> Cc: Ruifeng Wang <ruifeng.wang@arm.com>
> Cc: Jerin Jacob <jerinj@marvell.com>
> Cc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Cc: David Christensen <drc@linux.vnet.ibm.com>
>
> Signed-off-by: Ciara Power <ciara.power@intel.com>
>
> ---
> v3:
>   - Removed unnecessary define in generic rte_vect.h
>   - Changed default bitwidth for ARM to UINT16_MAX, to allow for SVE.
> v2: Changed default bitwidth for Arm to 128.
> ---
>  lib/librte_eal/arm/include/rte_vect.h      | 2 ++
>  lib/librte_eal/common/eal_common_options.c | 3 +++
>  lib/librte_eal/ppc/include/rte_vect.h      | 2 ++
>  lib/librte_eal/x86/include/rte_vect.h      | 2 ++
>  4 files changed, 9 insertions(+)
>
> diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h
> index 01c51712a1..a3508e69d5 100644
> --- a/lib/librte_eal/arm/include/rte_vect.h
> +++ b/lib/librte_eal/arm/include/rte_vect.h
> @@ -14,6 +14,8 @@
>  extern "C" {
>  #endif
>
> +#define RTE_DEFAULT_SIMD_BITWIDTH UINT16_MAX
> +
>  typedef int32x4_t xmm_t;
>
>  #define        XMM_SIZE        (sizeof(xmm_t))
> diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c
> index e9117a96af..d412cae89b 100644
> --- a/lib/librte_eal/common/eal_common_options.c
> +++ b/lib/librte_eal/common/eal_common_options.c
> @@ -35,6 +35,7 @@
>  #ifndef RTE_EXEC_ENV_WINDOWS
>  #include <rte_telemetry.h>
>  #endif
> +#include <rte_vect.h>
>
>  #include "eal_internal_cfg.h"
>  #include "eal_options.h"
> @@ -344,6 +345,8 @@ eal_reset_internal_config(struct internal_config *internal_cfg)
>         internal_cfg->user_mbuf_pool_ops_name = NULL;
>         CPU_ZERO(&internal_cfg->ctrl_cpuset);
>         internal_cfg->init_complete = 0;
> +       internal_cfg->max_simd_bitwidth.bitwidth = RTE_DEFAULT_SIMD_BITWIDTH;
> +       internal_cfg->max_simd_bitwidth.locked = 0;

Does the previous patch work without this one?
In any case, it seems a whole to me and reading one of Olivier's
questions on the default value, I would squash them together.



>  }
>
>  static int
> diff --git a/lib/librte_eal/ppc/include/rte_vect.h b/lib/librte_eal/ppc/include/rte_vect.h
> index b0545c878c..70fbd0c423 100644
> --- a/lib/librte_eal/ppc/include/rte_vect.h
> +++ b/lib/librte_eal/ppc/include/rte_vect.h
> @@ -15,6 +15,8 @@
>  extern "C" {
>  #endif
>
> +#define RTE_DEFAULT_SIMD_BITWIDTH 256
> +
>  typedef vector signed int xmm_t;
>
>  #define        XMM_SIZE        (sizeof(xmm_t))
> diff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/include/rte_vect.h
> index df5a607623..b1df75aca7 100644
> --- a/lib/librte_eal/x86/include/rte_vect.h
> +++ b/lib/librte_eal/x86/include/rte_vect.h
> @@ -35,6 +35,8 @@
>  extern "C" {
>  #endif
>
> +#define RTE_DEFAULT_SIMD_BITWIDTH 256
> +
>  typedef __m128i xmm_t;
>
>  #define        XMM_SIZE        (sizeof(xmm_t))
> --
> 2.17.1
>
diff mbox series

Patch

diff --git a/lib/librte_eal/arm/include/rte_vect.h b/lib/librte_eal/arm/include/rte_vect.h
index 01c51712a1..a3508e69d5 100644
--- a/lib/librte_eal/arm/include/rte_vect.h
+++ b/lib/librte_eal/arm/include/rte_vect.h
@@ -14,6 +14,8 @@ 
 extern "C" {
 #endif
 
+#define RTE_DEFAULT_SIMD_BITWIDTH UINT16_MAX
+
 typedef int32x4_t xmm_t;
 
 #define	XMM_SIZE	(sizeof(xmm_t))
diff --git a/lib/librte_eal/common/eal_common_options.c b/lib/librte_eal/common/eal_common_options.c
index e9117a96af..d412cae89b 100644
--- a/lib/librte_eal/common/eal_common_options.c
+++ b/lib/librte_eal/common/eal_common_options.c
@@ -35,6 +35,7 @@ 
 #ifndef RTE_EXEC_ENV_WINDOWS
 #include <rte_telemetry.h>
 #endif
+#include <rte_vect.h>
 
 #include "eal_internal_cfg.h"
 #include "eal_options.h"
@@ -344,6 +345,8 @@  eal_reset_internal_config(struct internal_config *internal_cfg)
 	internal_cfg->user_mbuf_pool_ops_name = NULL;
 	CPU_ZERO(&internal_cfg->ctrl_cpuset);
 	internal_cfg->init_complete = 0;
+	internal_cfg->max_simd_bitwidth.bitwidth = RTE_DEFAULT_SIMD_BITWIDTH;
+	internal_cfg->max_simd_bitwidth.locked = 0;
 }
 
 static int
diff --git a/lib/librte_eal/ppc/include/rte_vect.h b/lib/librte_eal/ppc/include/rte_vect.h
index b0545c878c..70fbd0c423 100644
--- a/lib/librte_eal/ppc/include/rte_vect.h
+++ b/lib/librte_eal/ppc/include/rte_vect.h
@@ -15,6 +15,8 @@ 
 extern "C" {
 #endif
 
+#define RTE_DEFAULT_SIMD_BITWIDTH 256
+
 typedef vector signed int xmm_t;
 
 #define	XMM_SIZE	(sizeof(xmm_t))
diff --git a/lib/librte_eal/x86/include/rte_vect.h b/lib/librte_eal/x86/include/rte_vect.h
index df5a607623..b1df75aca7 100644
--- a/lib/librte_eal/x86/include/rte_vect.h
+++ b/lib/librte_eal/x86/include/rte_vect.h
@@ -35,6 +35,8 @@ 
 extern "C" {
 #endif
 
+#define RTE_DEFAULT_SIMD_BITWIDTH 256
+
 typedef __m128i xmm_t;
 
 #define	XMM_SIZE	(sizeof(xmm_t))