diff mbox series

[v3,06/16] net/mlx5: fix dynamic mbuf offset lookup check

Message ID 20201103001407.2931963-7-thomas@monjalon.net (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series remove mbuf timestamp |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Thomas Monjalon Nov. 3, 2020, 12:13 a.m. UTC 
  The functions rte_mbuf_dynfield_lookup() and rte_mbuf_dynflag_lookup()
can return an offset starting with 0 or a negative error code.

In reality the first offsets are probably reserved forever,
but for the sake of strict API compliance,
the checks which considered 0 as an error are fixed.

Fixes: efa79e68c8cd ("net/mlx5: support fine grain dynamic flag")
Fixes: 3172c471b86f ("net/mlx5: prepare Tx queue structures to support timestamp")
Fixes: 0febfcce3693 ("net/mlx5: prepare Tx to support scheduling")
Cc: stable@dpdk.org

Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
---
 drivers/net/mlx5/mlx5_rxtx.c    | 4 ++--
 drivers/net/mlx5/mlx5_trigger.c | 2 +-
 drivers/net/mlx5/mlx5_txq.c     | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

Comments

Slava Ovsiienko Nov. 3, 2020, 8:12 a.m. UTC | #1 
> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Tuesday, November 3, 2020 2:14
> To: dev@dpdk.org
> Cc: ferruh.yigit@intel.com; david.marchand@redhat.com;
> bruce.richardson@intel.com; olivier.matz@6wind.com;
> andrew.rybchenko@oktetlabs.ru; jerinj@marvell.com; Slava Ovsiienko
> <viacheslavo@nvidia.com>; stable@dpdk.org; Matan Azrad
> <matan@nvidia.com>; Shahaf Shuler <shahafs@nvidia.com>; Ori Kam
> <orika@mellanox.com>
> Subject: [PATCH v3 06/16] net/mlx5: fix dynamic mbuf offset lookup check
> 
> The functions rte_mbuf_dynfield_lookup() and rte_mbuf_dynflag_lookup() can
> return an offset starting with 0 or a negative error code.
> 
> In reality the first offsets are probably reserved forever, but for the sake of
> strict API compliance, the checks which considered 0 as an error are fixed.
> 
> Fixes: efa79e68c8cd ("net/mlx5: support fine grain dynamic flag")
> Fixes: 3172c471b86f ("net/mlx5: prepare Tx queue structures to support
> timestamp")
> Fixes: 0febfcce3693 ("net/mlx5: prepare Tx to support scheduling")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>

> ---
>  drivers/net/mlx5/mlx5_rxtx.c    | 4 ++--
>  drivers/net/mlx5/mlx5_trigger.c | 2 +-
>  drivers/net/mlx5/mlx5_txq.c     | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c index
> b530ff421f..e86468b67a 100644
> --- a/drivers/net/mlx5/mlx5_rxtx.c
> +++ b/drivers/net/mlx5/mlx5_rxtx.c
> @@ -5661,9 +5661,9 @@ mlx5_select_tx_function(struct rte_eth_dev *dev)
>  	}
>  	if (tx_offloads & DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP &&
>  	    rte_mbuf_dynflag_lookup
> -			(RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL)
> > 0 &&
> +			(RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL)
> >= 0 &&
>  	    rte_mbuf_dynfield_lookup
> -			(RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) >
> 0) {
> +			(RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) >=
> 0) {
>  		/* Offload configured, dynamic entities registered. */
>  		olx |= MLX5_TXOFF_CONFIG_TXPP;
>  	}
> diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c
> index 7735f022a3..917b433c4a 100644
> --- a/drivers/net/mlx5/mlx5_trigger.c
> +++ b/drivers/net/mlx5/mlx5_trigger.c
> @@ -302,7 +302,7 @@ mlx5_dev_start(struct rte_eth_dev *dev)
>  	DRV_LOG(DEBUG, "port %u starting device", dev->data->port_id);
>  	fine_inline = rte_mbuf_dynflag_lookup
>  		(RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, NULL);
> -	if (fine_inline > 0)
> +	if (fine_inline >= 0)
>  		rte_net_mlx5_dynf_inline_mask = 1UL << fine_inline;
>  	else
>  		rte_net_mlx5_dynf_inline_mask = 0;
> diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index
> af84f5f72b..8ed2bcff7b 100644
> --- a/drivers/net/mlx5/mlx5_txq.c
> +++ b/drivers/net/mlx5/mlx5_txq.c
> @@ -1305,7 +1305,7 @@ mlx5_txq_dynf_timestamp_set(struct rte_eth_dev
> *dev)
> 
> 	(RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
>  	off = rte_mbuf_dynfield_lookup
>  				(RTE_MBUF_DYNFIELD_TIMESTAMP_NAME,
> NULL);
> -	if (nbit > 0 && off >= 0 && sh->txpp.refcnt)
> +	if (nbit >= 0 && off >= 0 && sh->txpp.refcnt)
>  		mask = 1ULL << nbit;
>  	for (i = 0; i != priv->txqs_n; ++i) {
>  		data = (*priv->txqs)[i];
> --
> 2.28.0
diff mbox series

Patch

diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index b530ff421f..e86468b67a 100644
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -5661,9 +5661,9 @@  mlx5_select_tx_function(struct rte_eth_dev *dev)
 	}
 	if (tx_offloads & DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP &&
 	    rte_mbuf_dynflag_lookup
-			(RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL) > 0 &&
+			(RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL) >= 0 &&
 	    rte_mbuf_dynfield_lookup
-			(RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) > 0) {
+			(RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) >= 0) {
 		/* Offload configured, dynamic entities registered. */
 		olx |= MLX5_TXOFF_CONFIG_TXPP;
 	}
diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c
index 7735f022a3..917b433c4a 100644
--- a/drivers/net/mlx5/mlx5_trigger.c
+++ b/drivers/net/mlx5/mlx5_trigger.c
@@ -302,7 +302,7 @@  mlx5_dev_start(struct rte_eth_dev *dev)
 	DRV_LOG(DEBUG, "port %u starting device", dev->data->port_id);
 	fine_inline = rte_mbuf_dynflag_lookup
 		(RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, NULL);
-	if (fine_inline > 0)
+	if (fine_inline >= 0)
 		rte_net_mlx5_dynf_inline_mask = 1UL << fine_inline;
 	else
 		rte_net_mlx5_dynf_inline_mask = 0;
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index af84f5f72b..8ed2bcff7b 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -1305,7 +1305,7 @@  mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev)
 				(RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL);
 	off = rte_mbuf_dynfield_lookup
 				(RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL);
-	if (nbit > 0 && off >= 0 && sh->txpp.refcnt)
+	if (nbit >= 0 && off >= 0 && sh->txpp.refcnt)
 		mask = 1ULL << nbit;
 	for (i = 0; i != priv->txqs_n; ++i) {
 		data = (*priv->txqs)[i];