diff mbox series

[v2,4/5] net/hns3: check PCI config space writes

Message ID 1604634716-43484-5-git-send-email-oulijun@huawei.com (mailing list archive)
State Changes Requested, archived
Delegated to: Ferruh Yigit
Headers
Series bugfix and cleanups for hns3 |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Lijun Ou Nov. 6, 2020, 3:51 a.m. UTC 
  Here adds a check for the return value when calling
rte_pci_write_config.

Coverity issue: 363714
Fixes: cea37e513329 ("net/hns3: fix FLR reset")
Cc: stable@dpdk.org

Signed-off-by: Lijun Ou <oulijun@huawei.com>
---
V1->V2:
- rte_pci_wirte_config -> rte_pci_write_config
---
 drivers/net/hns3/hns3_ethdev_vf.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

Comments

Ferruh Yigit Nov. 6, 2020, 4:45 p.m. UTC | #1 
On 11/6/2020 3:51 AM, Lijun Ou wrote:
> Here adds a check for the return value when calling
> rte_pci_write_config.
> 
> Coverity issue: 363714
> Fixes: cea37e513329 ("net/hns3: fix FLR reset")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Lijun Ou <oulijun@huawei.com>
> ---
> V1->V2:
> - rte_pci_wirte_config -> rte_pci_write_config
> ---
>   drivers/net/hns3/hns3_ethdev_vf.c | 10 +++++++---
>   1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c
> index 2e9bfda..2f6d91b 100644
> --- a/drivers/net/hns3/hns3_ethdev_vf.c
> +++ b/drivers/net/hns3/hns3_ethdev_vf.c
> @@ -139,7 +139,7 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
>   		ret = rte_pci_read_config(device, &control, sizeof(control),
>   				    (pos + PCI_MSIX_FLAGS));
>   		if (ret < 0) {
> -			PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
> +			PMD_INIT_LOG(ERR, "failed to read PCI offset 0x%x",

Can you please drop this unrelated change from the patch?

>   				     (pos + PCI_MSIX_FLAGS));
>   			return -ENXIO;
>   		}
> @@ -148,8 +148,12 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
>   			control |= PCI_MSIX_FLAGS_ENABLE;
>   		else
>   			control &= ~PCI_MSIX_FLAGS_ENABLE;
> -		rte_pci_write_config(device, &control, sizeof(control),
> -				     (pos + PCI_MSIX_FLAGS));
> +		ret = rte_pci_write_config(device, &control, sizeof(control),
> +					  (pos + PCI_MSIX_FLAGS));
> +		if (ret < 0) {
> +			PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
> +				    (pos + PCI_MSIX_FLAGS));
> +		}
>   		return 0;
>   	}
>   	return -ENXIO;
>
Lijun Ou Nov. 9, 2020, 1:44 p.m. UTC | #2 
在 2020/11/7 0:45, Ferruh Yigit 写道:
> On 11/6/2020 3:51 AM, Lijun Ou wrote:
>> Here adds a check for the return value when calling
>> rte_pci_write_config.
>>
>> Coverity issue: 363714
>> Fixes: cea37e513329 ("net/hns3: fix FLR reset")
>> Cc: stable@dpdk.org
>>
>> Signed-off-by: Lijun Ou <oulijun@huawei.com>
>> ---
>> V1->V2:
>> - rte_pci_wirte_config -> rte_pci_write_config
>> ---
>>   drivers/net/hns3/hns3_ethdev_vf.c | 10 +++++++---
>>   1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/net/hns3/hns3_ethdev_vf.c 
>> b/drivers/net/hns3/hns3_ethdev_vf.c
>> index 2e9bfda..2f6d91b 100644
>> --- a/drivers/net/hns3/hns3_ethdev_vf.c
>> +++ b/drivers/net/hns3/hns3_ethdev_vf.c
>> @@ -139,7 +139,7 @@ hns3vf_enable_msix(const struct rte_pci_device 
>> *device, bool op)
>>           ret = rte_pci_read_config(device, &control, sizeof(control),
>>                       (pos + PCI_MSIX_FLAGS));
>>           if (ret < 0) {
>> -            PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
>> +            PMD_INIT_LOG(ERR, "failed to read PCI offset 0x%x",
> 
> Can you please drop this unrelated change from the patch?
> 
Yes. I will fix it
>>                        (pos + PCI_MSIX_FLAGS));
>>               return -ENXIO;
>>           }
>> @@ -148,8 +148,12 @@ hns3vf_enable_msix(const struct rte_pci_device 
>> *device, bool op)
>>               control |= PCI_MSIX_FLAGS_ENABLE;
>>           else
>>               control &= ~PCI_MSIX_FLAGS_ENABLE;
>> -        rte_pci_write_config(device, &control, sizeof(control),
>> -                     (pos + PCI_MSIX_FLAGS));
>> +        ret = rte_pci_write_config(device, &control, sizeof(control),
>> +                      (pos + PCI_MSIX_FLAGS));
>> +        if (ret < 0) {
>> +            PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
>> +                    (pos + PCI_MSIX_FLAGS));
>> +        }
>>           return 0;
>>       }
>>       return -ENXIO;
>>
> 
> .
>
diff mbox series

Patch

diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c
index 2e9bfda..2f6d91b 100644
--- a/drivers/net/hns3/hns3_ethdev_vf.c
+++ b/drivers/net/hns3/hns3_ethdev_vf.c
@@ -139,7 +139,7 @@  hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 		ret = rte_pci_read_config(device, &control, sizeof(control),
 				    (pos + PCI_MSIX_FLAGS));
 		if (ret < 0) {
-			PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
+			PMD_INIT_LOG(ERR, "failed to read PCI offset 0x%x",
 				     (pos + PCI_MSIX_FLAGS));
 			return -ENXIO;
 		}
@@ -148,8 +148,12 @@  hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
 			control |= PCI_MSIX_FLAGS_ENABLE;
 		else
 			control &= ~PCI_MSIX_FLAGS_ENABLE;
-		rte_pci_write_config(device, &control, sizeof(control),
-				     (pos + PCI_MSIX_FLAGS));
+		ret = rte_pci_write_config(device, &control, sizeof(control),
+					  (pos + PCI_MSIX_FLAGS));
+		if (ret < 0) {
+			PMD_INIT_LOG(ERR, "failed to write PCI offset 0x%x",
+				    (pos + PCI_MSIX_FLAGS));
+		}
 		return 0;
 	}
 	return -ENXIO;