diff mbox series

[09/17] common/mlx5: enhance page size configuration

Message ID	1608205475-20067-10-git-send-email-michaelba@nvidia.com (mailing list archive)
State	Superseded, archived
Delegated to:	Raslan Darawsheh
Headers	From: Michael Baum <michaelba@nvidia.com> To: dev@dpdk.org Cc: Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com> Date: Thu, 17 Dec 2020 11:44:27 +0000 Message-Id: <1608205475-20067-10-git-send-email-michaelba@nvidia.com> In-Reply-To: <1608205475-20067-1-git-send-email-michaelba@nvidia.com> References: <1608205475-20067-1-git-send-email-michaelba@nvidia.com> Subject: [dpdk-dev] [PATCH 09/17] common/mlx5: enhance page size configuration Precedence: list Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org>
Series	common/mlx5: share DevX resources creations \| [00/17] common/mlx5: share DevX resources creations [01/17] net/mlx5: fix ASO SQ creation error flow [02/17] common/mlx5: share DevX CQ creation [03/17] regex/mlx5: move DevX CQ creation to common [04/17] vdpa/mlx5: move DevX CQ creation to common [05/17] net/mlx5: move rearm and clock queue CQ creation to common [06/17] net/mlx5: move ASO CQ creation to common [07/17] net/mlx5: move Tx CQ creation to common [08/17] net/mlx5: move Rx CQ creation to common [09/17] common/mlx5: enhance page size configuration [10/17] common/mlx5: share DevX SQ creation [11/17] regex/mlx5: move DevX SQ creation to common [12/17] net/mlx5: move rearm and clock queue SQ creation to common [13/17] net/mlx5: move Tx SQ creation to common [14/17] net/mlx5: move ASO SQ creation to common [15/17] common/mlx5: share DevX RQ creation [16/17] net/mlx5: move Rx RQ creation to common [17/17] common/mlx5: remove doorbell allocation API

Checks

Context	Check	Description
ci/checkpatch	success	coding style OK

Commit Message

Michael Baum Dec. 17, 2020, 11:44 a.m. UTC

  The PRM calculates page size in 4K, so need to reduce the log_wq_pg_sz
attribute.

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c | 53 ++++++++++++++++--------------------
 drivers/net/mlx5/mlx5_devx.c         | 13 +++++----
 2 files changed, 30 insertions(+), 36 deletions(-)

diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 9c1d188..09e204b 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -268,9 +268,8 @@  struct mlx5_devx_obj *
 	MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 	MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 	MLX5_SET(mkc, mkc, relaxed_ordering_write,
-		attr->relaxed_ordering_write);
-	MLX5_SET(mkc, mkc, relaxed_ordering_read,
-		attr->relaxed_ordering_read);
+		 attr->relaxed_ordering_write);
+	MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
 	MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 	MLX5_SET64(mkc, mkc, len, attr->size);
 	mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
@@ -308,7 +307,7 @@  struct mlx5_devx_obj *
 	if (status) {
 		int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 
-		DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
+		DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
 			syndrome);
 	}
 	return status;
@@ -374,8 +373,7 @@  struct mlx5_devx_obj *
 	syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 	if (status) {
 		DRV_LOG(DEBUG, "Failed to query NIC vport context, "
-			"status %x, syndrome = %x",
-			status, syndrome);
+			"status %x, syndrome = %x", status, syndrome);
 		return -1;
 	}
 	vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
@@ -662,8 +660,7 @@  struct mlx5_devx_obj *
 	syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 	if (status) {
 		DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
-			"status %x, syndrome = %x",
-			status, syndrome);
+			"status %x, syndrome = %x", status, syndrome);
 		return -1;
 	}
 	hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
@@ -683,11 +680,11 @@  struct mlx5_devx_obj *
 		(cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 	attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 	attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
-			relaxed_ordering_write);
+						relaxed_ordering_write);
 	attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
-			relaxed_ordering_read);
+					       relaxed_ordering_read);
 	attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
-			access_register_user);
+					      access_register_user);
 	attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 					  eth_net_offloads);
 	attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
@@ -730,8 +727,7 @@  struct mlx5_devx_obj *
 			goto error;
 		if (status) {
 			DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
-				" status %x, syndrome = %x",
-				status, syndrome);
+				" status %x, syndrome = %x", status, syndrome);
 			return -1;
 		}
 		hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
@@ -761,17 +757,14 @@  struct mlx5_devx_obj *
 		 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 		 MLX5_HCA_CAP_OPMOD_GET_CUR);
 
-	rc = mlx5_glue->devx_general_cmd(ctx,
-					 in, sizeof(in),
-					 out, sizeof(out));
+	rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 	if (rc)
 		goto error;
 	status = MLX5_GET(query_hca_cap_out, out, status);
 	syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 	if (status) {
 		DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
-			"status %x, syndrome = %x",
-			status, syndrome);
+			"status %x, syndrome = %x", status, syndrome);
 		attr->log_max_ft_sampler_num = 0;
 		return -1;
 	}
@@ -788,9 +781,7 @@  struct mlx5_devx_obj *
 		 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 		 MLX5_HCA_CAP_OPMOD_GET_CUR);
 
-	rc = mlx5_glue->devx_general_cmd(ctx,
-					 in, sizeof(in),
-					 out, sizeof(out));
+	rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 	if (rc) {
 		attr->eth_net_offloads = 0;
 		goto error;
@@ -799,8 +790,7 @@  struct mlx5_devx_obj *
 	syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 	if (status) {
 		DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
-			"status %x, syndrome = %x",
-			status, syndrome);
+			"status %x, syndrome = %x", status, syndrome);
 		attr->eth_net_offloads = 0;
 		return -1;
 	}
@@ -916,7 +906,9 @@  struct mlx5_devx_obj *
 	MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
 	MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
 	MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
-	MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
+	if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
+		MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
+			 wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
 	MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
 	MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
 	MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
@@ -1562,13 +1554,13 @@  struct mlx5_devx_obj *
 	MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
 	MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
 	MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
-	MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size -
-		 MLX5_ADAPTER_PAGE_SHIFT);
+	if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
+		MLX5_SET(cqc, cqctx, log_page_size,
+			 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
 	MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
 	MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
 	MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
-	MLX5_SET(cqc, cqctx, mini_cqe_res_format,
-		 attr->mini_cqe_res_format);
+	MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
 	MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
 		 attr->mini_cqe_res_format_ext);
 	MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
@@ -1798,8 +1790,9 @@  struct mlx5_devx_obj *
 	if (attr->uar_index) {
 		MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
 		MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
-		MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size -
-			 MLX5_ADAPTER_PAGE_SHIFT);
+		if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
+			MLX5_SET(qpc, qpc, log_page_size,
+				 attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
 		if (attr->sq_size) {
 			MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
 			MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c
index 6ad70f2..fe103a7 100644
--- a/drivers/net/mlx5/mlx5_devx.c
+++ b/drivers/net/mlx5/mlx5_devx.c
@@ -320,7 +320,13 @@ 
 	uint32_t log_wqe_size = 0;
 	void *buf = NULL;
 	struct mlx5_devx_obj *rq;
+	size_t alignment = MLX5_WQE_BUF_ALIGNMENT;
 
+	if (alignment == (size_t)-1) {
+		DRV_LOG(ERR, "Failed to get mem page size");
+		rte_errno = ENOMEM;
+		return NULL;
+	}
 	/* Fill RQ attributes. */
 	rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
 	rq_attr.flush_in_error_en = 1;
@@ -347,15 +353,10 @@ 
 	log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
 	rq_attr.wq_attr.log_wq_stride = log_wqe_size;
 	rq_attr.wq_attr.log_wq_sz = rxq_data->elts_n - rxq_data->sges_n;
+	rq_attr.wq_attr.log_wq_pg_sz = log2above(alignment);
 	/* Calculate and allocate WQ memory space. */
 	wqe_size = 1 << log_wqe_size; /* round up power of two.*/
 	wq_size = wqe_n * wqe_size;
-	size_t alignment = MLX5_WQE_BUF_ALIGNMENT;
-	if (alignment == (size_t)-1) {
-		DRV_LOG(ERR, "Failed to get mem page size");
-		rte_errno = ENOMEM;
-		return NULL;
-	}
 	buf = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, wq_size,
 			  alignment, rxq_ctrl->socket);
 	if (!buf)