@@ -167,7 +167,7 @@ Runtime Config Options
With the above configuration, higig2 will be enabled on that port and the
traffic on this port should be higig2 traffic only. Supported switch header
- types are "higig2", "dsa", "chlen90b" and "chlen24b".
+ types are "chlen24b", "chlen90b", "dsa", "exdsa", "higig2" and "vlan_exdsa".
- ``RSS tag as XOR`` (default ``0``)
@@ -362,6 +362,8 @@ Patterns:
+----+--------------------------------+
| 24 | RTE_FLOW_ITEM_TYPE_HIGIG2 |
+----+--------------------------------+
+ | 25 | RTE_FLOW_ITEM_TYPE_RAW |
+ +----+--------------------------------+
.. note::
@@ -417,3 +419,38 @@ Actions:
+----+-----------------------------------------+
| 5 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP |
+----+-----------------------------------------+
+
+Custom protocols supported in RTE Flow
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols.
+
+* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level.
+* ``NGIO`` can be parsed at L3 level.
+
+For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the
+respective switch header.
+
+For example::
+
+ -a 0002:02:00.0,switch_header="vlan_exdsa"
+
+The below fields of ``struct rte_flow_item_raw`` shall be used to specify the
+pattern.
+
+- ``relative`` Selects the layer at which parsing is done.
+
+ - 0 for ``exdsa`` and ``vlan_exdsa``.
+
+ - 1 for ``NGIO``.
+
+- ``offset`` The offset in the header where the pattern should be matched.
+- ``length`` Length of the pattern.
+- ``pattern`` Pattern as a byte string.
+
+Example usage in testpmd::
+
+ ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \
+ --rx-offloads=0x00080000 --rxq 8 --txq 8
+ testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \
+ spec ab pattern mask ab offset is 4 / end actions queue index 1 / end
@@ -205,6 +205,7 @@ enum npc_kpu_lb_ltype {
NPC_LT_LB_EXDSA,
NPC_LT_LB_EXDSA_VLAN,
NPC_LT_LB_FDSA,
+ NPC_LT_LB_VLAN_EXDSA,
NPC_LT_LB_CUSTOM0 = 0xE,
NPC_LT_LB_CUSTOM1 = 0xF,
};
@@ -220,6 +221,7 @@ enum npc_kpu_lc_ltype {
NPC_LT_LC_MPLS,
NPC_LT_LC_NSH,
NPC_LT_LC_FCOE,
+ NPC_LT_LC_NGIO,
NPC_LT_LC_CUSTOM0 = 0xE,
NPC_LT_LC_CUSTOM1 = 0xF,
};
@@ -354,11 +354,13 @@ struct ready_msg_rsp {
};
enum npc_pkind_type {
- NPC_RX_CHLEN24B_PKIND = 57ULL,
+ NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
+ NPC_RX_CHLEN24B_PKIND,
NPC_RX_CPT_HDR_PKIND,
NPC_RX_CHLEN90B_PKIND,
NPC_TX_HIGIG_PKIND,
NPC_RX_HIGIG_PKIND,
+ NPC_RX_EXDSA_PKIND,
NPC_RX_EDSA_PKIND,
NPC_TX_DEF_PKIND,
};
@@ -373,6 +375,8 @@ struct npc_set_pkind {
#define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)
#define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)
#define OTX2_PRIV_FLAGS_FDSA BIT_ULL(3)
+#define OTX2_PRIV_FLAGS_EXDSA BIT_ULL(4)
+#define OTX2_PRIV_FLAGS_VLAN_EXDSA BIT_ULL(5)
#define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
uint64_t __otx2_io mode;
#define PKIND_TX BIT_ULL(0)
@@ -122,6 +122,14 @@ nix_lf_switch_header_type_enable(struct otx2_eth_dev *dev, bool enable)
OTX2_PRIV_FLAGS_CH_LEN_24B) {
req->mode = OTX2_PRIV_FLAGS_CUSTOM;
req->pkind = NPC_RX_CHLEN24B_PKIND;
+ } else if (dev->npc_flow.switch_header_type ==
+ OTX2_PRIV_FLAGS_EXDSA) {
+ req->mode = OTX2_PRIV_FLAGS_CUSTOM;
+ req->pkind = NPC_RX_EXDSA_PKIND;
+ } else if (dev->npc_flow.switch_header_type ==
+ OTX2_PRIV_FLAGS_VLAN_EXDSA) {
+ req->mode = OTX2_PRIV_FLAGS_CUSTOM;
+ req->pkind = NPC_RX_VLAN_EXDSA_PKIND;
}
if (enable == 0)
@@ -119,6 +119,12 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args)
if (strcmp(value, "chlen24b") == 0)
*(uint16_t *)extra_args = OTX2_PRIV_FLAGS_CH_LEN_24B;
+ if (strcmp(value, "exdsa") == 0)
+ *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_EXDSA;
+
+ if (strcmp(value, "vlan_exdsa") == 0)
+ *(uint16_t *)extra_args = OTX2_PRIV_FLAGS_VLAN_EXDSA;
+
return 0;
}
@@ -30,6 +30,7 @@ enum {
#define NPC_IH_LENGTH 8
#define NPC_TPID_LENGTH 2
#define NPC_HIGIG2_LENGTH 16
+#define NPC_MAX_RAW_ITEM_LEN 16
#define NPC_COUNTER_NONE (-1)
/* 32 bytes from LDATA_CFG & 32 bytes from FLAGS_CFG */
#define NPC_MAX_EXTRACT_DATA_LEN (64)
@@ -74,11 +74,14 @@ const char *ltype_str[NPC_MAX_LID][NPC_MAX_LT] = {
[NPC_LID_LB][NPC_LT_LB_CTAG] = "LB_CTAG",
[NPC_LID_LB][NPC_LT_LB_STAG_QINQ] = "LB_STAG_QINQ",
[NPC_LID_LB][NPC_LT_LB_ETAG] = "LB_ETAG",
+ [NPC_LID_LB][NPC_LT_LB_EXDSA] = "LB_EXDSA",
+ [NPC_LID_LB][NPC_LT_LB_VLAN_EXDSA] = "LB_VLAN_EXDSA",
[NPC_LID_LC][0] = "NONE",
[NPC_LID_LC][NPC_LT_LC_IP] = "LC_IP",
[NPC_LID_LC][NPC_LT_LC_IP6] = "LC_IP6",
[NPC_LID_LC][NPC_LT_LC_ARP] = "LC_ARP",
[NPC_LID_LC][NPC_LT_LC_IP6_EXT] = "LC_IP6_EXT",
+ [NPC_LID_LC][NPC_LT_LC_NGIO] = "LC_NGIO",
[NPC_LID_LD][0] = "NONE",
[NPC_LID_LD][NPC_LT_LD_ICMP] = "LD_ICMP",
[NPC_LID_LD][NPC_LT_LD_ICMP6] = "LD_ICMP6",
@@ -489,13 +489,45 @@ flow_check_lc_ip_tunnel(struct otx2_parse_state *pst)
pst->tunnel = 1;
}
+static int
+otx2_flow_raw_item_prepare(const struct rte_flow_item_raw *raw_spec,
+ const struct rte_flow_item_raw *raw_mask,
+ struct otx2_flow_item_info *info,
+ uint8_t *spec_buf, uint8_t *mask_buf)
+{
+ uint32_t custom_hdr_size = 0;
+
+ memset(spec_buf, 0, NPC_MAX_RAW_ITEM_LEN);
+ memset(mask_buf, 0, NPC_MAX_RAW_ITEM_LEN);
+ custom_hdr_size = raw_spec->offset + raw_spec->length;
+
+ memcpy(spec_buf + raw_spec->offset, raw_spec->pattern,
+ raw_spec->length);
+
+ if (raw_mask->pattern) {
+ memcpy(mask_buf + raw_spec->offset, raw_mask->pattern,
+ raw_spec->length);
+ } else {
+ memset(mask_buf + raw_spec->offset, 0xFF, raw_spec->length);
+ }
+
+ info->len = custom_hdr_size;
+ info->spec = spec_buf;
+ info->mask = mask_buf;
+
+ return 0;
+}
+
/* Outer IPv4, Outer IPv6, MPLS, ARP */
int
otx2_flow_parse_lc(struct otx2_parse_state *pst)
{
+ uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];
+ uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];
uint8_t hw_mask[NPC_MAX_EXTRACT_DATA_LEN];
+ const struct rte_flow_item_raw *raw_spec;
struct otx2_flow_item_info info;
- int lid, lt;
+ int lid, lt, len;
int rc;
if (pst->pattern->type == RTE_FLOW_ITEM_TYPE_MPLS)
@@ -531,6 +563,30 @@ otx2_flow_parse_lc(struct otx2_parse_state *pst)
info.len = sizeof(struct rte_flow_item_ipv6_ext);
info.hw_hdr_len = 40;
break;
+ case RTE_FLOW_ITEM_TYPE_RAW:
+ raw_spec = pst->pattern->spec;
+ if (!raw_spec->relative)
+ return 0;
+
+ len = raw_spec->length + raw_spec->offset;
+ if (len > NPC_MAX_RAW_ITEM_LEN) {
+ rte_flow_error_set(pst->error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM, NULL,
+ "Spec length too big");
+ return -rte_errno;
+ }
+
+ otx2_flow_raw_item_prepare((const struct rte_flow_item_raw *)
+ pst->pattern->spec,
+ (const struct rte_flow_item_raw *)
+ pst->pattern->mask, &info,
+ raw_spec_buf, raw_mask_buf);
+
+ lid = NPC_LID_LC;
+ lt = NPC_LT_LC_NGIO;
+ info.hw_mask = &hw_mask;
+ otx2_flow_get_hw_supp_mask(pst, &info, lid, lt);
+ break;
default:
/* No match at this layer */
return 0;
@@ -552,10 +608,13 @@ int
otx2_flow_parse_lb(struct otx2_parse_state *pst)
{
const struct rte_flow_item *pattern = pst->pattern;
+ uint8_t raw_spec_buf[NPC_MAX_RAW_ITEM_LEN];
+ uint8_t raw_mask_buf[NPC_MAX_RAW_ITEM_LEN];
const struct rte_flow_item *last_pattern;
+ const struct rte_flow_item_raw *raw_spec;
char hw_mask[NPC_MAX_EXTRACT_DATA_LEN];
struct otx2_flow_item_info info;
- int lid, lt, lflags;
+ int lid, lt, lflags, len;
int nr_vlans = 0;
int rc;
@@ -638,13 +697,44 @@ otx2_flow_parse_lb(struct otx2_parse_state *pst)
info.def_mask = &rte_flow_item_e_tag_mask;
info.len = sizeof(struct rte_flow_item_e_tag);
+ } else if (pst->pattern->type == RTE_FLOW_ITEM_TYPE_RAW) {
+ raw_spec = pst->pattern->spec;
+ if (raw_spec->relative)
+ return 0;
+ len = raw_spec->length + raw_spec->offset;
+ if (len > NPC_MAX_RAW_ITEM_LEN) {
+ rte_flow_error_set(pst->error, EINVAL,
+ RTE_FLOW_ERROR_TYPE_ITEM, NULL,
+ "Spec length too big");
+ return -rte_errno;
+ }
+
+ if (pst->npc->switch_header_type ==
+ OTX2_PRIV_FLAGS_VLAN_EXDSA) {
+ lt = NPC_LT_LB_VLAN_EXDSA;
+ } else if (pst->npc->switch_header_type ==
+ OTX2_PRIV_FLAGS_EXDSA) {
+ lt = NPC_LT_LB_EXDSA;
+ } else {
+ rte_flow_error_set(pst->error, ENOTSUP,
+ RTE_FLOW_ERROR_TYPE_ITEM, NULL,
+ "exdsa or vlan_exdsa not enabled on"
+ " port");
+ return -rte_errno;
+ }
+
+ otx2_flow_raw_item_prepare((const struct rte_flow_item_raw *)
+ pst->pattern->spec,
+ (const struct rte_flow_item_raw *)
+ pst->pattern->mask, &info,
+ raw_spec_buf, raw_mask_buf);
+
+ info.hw_hdr_len = 0;
} else {
return 0;
}
info.hw_mask = &hw_mask;
- info.spec = NULL;
- info.mask = NULL;
otx2_flow_get_hw_supp_mask(pst, &info, lid, lt);
rc = otx2_flow_parse_item_basic(pst->pattern, &info, pst->error);
@@ -656,6 +746,7 @@ otx2_flow_parse_lb(struct otx2_parse_state *pst)
return otx2_flow_update_parse_state(pst, &info, lid, lt, lflags);
}
+
int
otx2_flow_parse_la(struct otx2_parse_state *pst)
{
@@ -390,7 +390,8 @@ otx2_flow_parse_item_basic(const struct rte_flow_item *item,
}
/* We have valid spec */
- info->spec = item->spec;
+ if (item->type != RTE_FLOW_ITEM_TYPE_RAW)
+ info->spec = item->spec;
/* If mask is not set, use default mask, err if default mask is
* also NULL.
@@ -405,7 +406,8 @@ otx2_flow_parse_item_basic(const struct rte_flow_item *item,
}
info->mask = info->def_mask;
} else {
- info->mask = item->mask;
+ if (item->type != RTE_FLOW_ITEM_TYPE_RAW)
+ info->mask = item->mask;
}
/* mask specified must be subset of hw supported mask