[v18,3/3] config: fix Arm implementer and its SoCs
Checks
Commit Message
Fix the implementer and part number of DPAA and ARMADA SoCs.
The current values of 16 cores and 1 NUMA node don't cover all SoCs from
the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes.
Increase these to 64 and 4 to widen the coverage.
Add configuration to SoC options where smaller values are needed.
Fixes: 6ec78c2463ac ("build: add meson support for dpaaX platforms")
Cc: hemant.agrawal@nxp.com
Fixes: dd1cd845c102 ("config: add Marvell ARMADA based on armv8-a")
Cc: lironh@marvell.com
Fixes: d97108a33231 ("config: change defaults of armv8")
Cc: yskoh@mellanox.com
Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Liron Himi <lironh@marvell.com>
Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
config/arm/meson.build | 60 +++++++++++++++++++-----------------------
1 file changed, 27 insertions(+), 33 deletions(-)
Comments
> -----Original Message-----
> From: Juraj Linkeš <juraj.linkes@pantheon.tech>
> Sent: Friday, April 9, 2021 2:36 PM
> To: bruce.richardson@intel.com; Ruifeng Wang <Ruifeng.Wang@arm.com>;
> Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>; Phil Yang
> <Phil.Yang@arm.com>; vcchunga@amazon.com; Dharmik Thakkar
> <Dharmik.Thakkar@arm.com>; jerinjacobk@gmail.com;
> hemant.agrawal@nxp.com; Ajit Khaparde (ajit.khaparde@broadcom.com)
> <ajit.khaparde@broadcom.com>; ferruh.yigit@intel.com;
> aboyer@pensando.io
> Cc: dev@dpdk.org; Juraj Linkeš <juraj.linkes@pantheon.tech>;
> lironh@marvell.com; yskoh@mellanox.com
> Subject: [PATCH v18 3/3] config: fix Arm implementer and its SoCs
>
> Fix the implementer and part number of DPAA and ARMADA SoCs.
> The current values of 16 cores and 1 NUMA node don't cover all SoCs from
> the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA nodes.
> Increase these to 64 and 4 to widen the coverage.
> Add configuration to SoC options where smaller values are needed.
>
> Fixes: 6ec78c2463ac ("build: add meson support for dpaaX platforms")
> Cc: hemant.agrawal@nxp.com
> Fixes: dd1cd845c102 ("config: add Marvell ARMADA based on armv8-a")
> Cc: lironh@marvell.com
> Fixes: d97108a33231 ("config: change defaults of armv8")
> Cc: yskoh@mellanox.com
>
> Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Reviewed-by: Liron Himi <lironh@marvell.com>
> Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> ---
> config/arm/meson.build | 60 +++++++++++++++++++-----------------------
> 1 file changed, 27 insertions(+), 33 deletions(-)
>
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> 6fcbbf2ebc..53577267a6 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -56,7 +56,8 @@ part_number_config_arm = {
> ['RTE_MACHINE', '"neoverse-n1"'],
> ['RTE_ARM_FEATURE_ATOMICS', true],
> ['RTE_MAX_MEM_MB', 1048576],
> - ['RTE_MAX_LCORE', 80]
> + ['RTE_MAX_LCORE', 80],
> + ['RTE_MAX_NUMA_NODES', 1]
Ampere Altra that based on Neoverse-n1 has 2-socket server.
So MAX_LCORE should be updated to 160, and MAX_NUMA_NODES should be updated to 2.
> ]
> },
> '0xd49': {
> @@ -64,7 +65,8 @@ part_number_config_arm = {
> 'flags': [
> ['RTE_MACHINE', '"neoverse-n2"'],
> ['RTE_ARM_FEATURE_ATOMICS', true],
> - ['RTE_MAX_LCORE', 64]
> + ['RTE_MAX_LCORE', 64],
> + ['RTE_MAX_NUMA_NODES', 1]
> ]
> }
> }
> -----Original Message-----
> From: Ruifeng Wang <Ruifeng.Wang@arm.com>
> Sent: Friday, April 9, 2021 10:27 AM
> To: Juraj Linkeš <juraj.linkes@pantheon.tech>; bruce.richardson@intel.com;
> Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>;
> vcchunga@amazon.com; Dharmik Thakkar <Dharmik.Thakkar@arm.com>;
> jerinjacobk@gmail.com; hemant.agrawal@nxp.com; Ajit Khaparde
> (ajit.khaparde@broadcom.com) <ajit.khaparde@broadcom.com>;
> ferruh.yigit@intel.com; aboyer@pensando.io
> Cc: dev@dpdk.org; lironh@marvell.com; yskoh@mellanox.com; nd
> <nd@arm.com>
> Subject: RE: [PATCH v18 3/3] config: fix Arm implementer and its SoCs
>
> > -----Original Message-----
> > From: Juraj Linkeš <juraj.linkes@pantheon.tech>
> > Sent: Friday, April 9, 2021 2:36 PM
> > To: bruce.richardson@intel.com; Ruifeng Wang <Ruifeng.Wang@arm.com>;
> > Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>; Phil Yang
> > <Phil.Yang@arm.com>; vcchunga@amazon.com; Dharmik Thakkar
> > <Dharmik.Thakkar@arm.com>; jerinjacobk@gmail.com;
> > hemant.agrawal@nxp.com; Ajit Khaparde (ajit.khaparde@broadcom.com)
> > <ajit.khaparde@broadcom.com>; ferruh.yigit@intel.com;
> > aboyer@pensando.io
> > Cc: dev@dpdk.org; Juraj Linkeš <juraj.linkes@pantheon.tech>;
> > lironh@marvell.com; yskoh@mellanox.com
> > Subject: [PATCH v18 3/3] config: fix Arm implementer and its SoCs
> >
> > Fix the implementer and part number of DPAA and ARMADA SoCs.
> > The current values of 16 cores and 1 NUMA node don't cover all SoCs
> > from the Arm implementer, e.g. Taishan 2280 has 64 cores and 4 NUMA
> nodes.
> > Increase these to 64 and 4 to widen the coverage.
> > Add configuration to SoC options where smaller values are needed.
> >
> > Fixes: 6ec78c2463ac ("build: add meson support for dpaaX platforms")
> > Cc: hemant.agrawal@nxp.com
> > Fixes: dd1cd845c102 ("config: add Marvell ARMADA based on armv8-a")
> > Cc: lironh@marvell.com
> > Fixes: d97108a33231 ("config: change defaults of armv8")
> > Cc: yskoh@mellanox.com
> >
> > Signed-off-by: Juraj Linkeš <juraj.linkes@pantheon.tech>
> > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> > Reviewed-by: Liron Himi <lironh@marvell.com>
> > Acked-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
> > Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
> > ---
> > config/arm/meson.build | 60
> > +++++++++++++++++++-----------------------
> > 1 file changed, 27 insertions(+), 33 deletions(-)
> >
> > diff --git a/config/arm/meson.build b/config/arm/meson.build index
> > 6fcbbf2ebc..53577267a6 100644
> > --- a/config/arm/meson.build
> > +++ b/config/arm/meson.build
> > @@ -56,7 +56,8 @@ part_number_config_arm = {
> > ['RTE_MACHINE', '"neoverse-n1"'],
> > ['RTE_ARM_FEATURE_ATOMICS', true],
> > ['RTE_MAX_MEM_MB', 1048576],
> > - ['RTE_MAX_LCORE', 80]
> > + ['RTE_MAX_LCORE', 80],
> > + ['RTE_MAX_NUMA_NODES', 1]
>
> Ampere Altra that based on Neoverse-n1 has 2-socket server.
> So MAX_LCORE should be updated to 160, and MAX_NUMA_NODES should be
> updated to 2.
>
Ok, will update.
> > ]
> > },
> > '0xd49': {
> > @@ -64,7 +65,8 @@ part_number_config_arm = {
> > 'flags': [
> > ['RTE_MACHINE', '"neoverse-n2"'],
> > ['RTE_ARM_FEATURE_ATOMICS', true],
> > - ['RTE_MAX_LCORE', 64]
> > + ['RTE_MAX_LCORE', 64],
> > + ['RTE_MAX_NUMA_NODES', 1]
> > ]
> > }
> > }
@@ -56,7 +56,8 @@ part_number_config_arm = {
['RTE_MACHINE', '"neoverse-n1"'],
['RTE_ARM_FEATURE_ATOMICS', true],
['RTE_MAX_MEM_MB', 1048576],
- ['RTE_MAX_LCORE', 80]
+ ['RTE_MAX_LCORE', 80],
+ ['RTE_MAX_NUMA_NODES', 1]
]
},
'0xd49': {
@@ -64,7 +65,8 @@ part_number_config_arm = {
'flags': [
['RTE_MACHINE', '"neoverse-n2"'],
['RTE_ARM_FEATURE_ATOMICS', true],
- ['RTE_MAX_LCORE', 64]
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 1]
]
}
}
@@ -74,8 +76,8 @@ implementer_arm = {
['RTE_MACHINE', '"armv8a"'],
['RTE_USE_C11_MEM_MODEL', true],
['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_LCORE', 16],
- ['RTE_MAX_NUMA_NODES', 1]
+ ['RTE_MAX_LCORE', 64],
+ ['RTE_MAX_NUMA_NODES', 4]
],
'part_number_config': part_number_config_arm
}
@@ -157,39 +159,13 @@ implementer_qualcomm = {
}
}
-implementer_marvell = {
- 'description': 'Marvell ARMADA',
- 'flags': [
- ['RTE_MACHINE', '"armv8a"'],
- ['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_LCORE', 16],
- ['RTE_MAX_NUMA_NODES', 1]
- ],
- 'part_number_config': part_number_config_arm
-}
-
-implementer_dpaa = {
- 'description': 'NXP DPAA',
- 'flags': [
- ['RTE_MACHINE', '"dpaa"'],
- ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
- ['RTE_USE_C11_MEM_MODEL', true],
- ['RTE_CACHE_LINE_SIZE', 64],
- ['RTE_MAX_LCORE', 16],
- ['RTE_MAX_NUMA_NODES', 1]
- ],
- 'part_number_config': part_number_config_arm
-}
-
## Arm implementers (ID from MIDR in Arm Architecture Reference Manual)
implementers = {
'generic': implementer_generic,
'0x41': implementer_arm,
'0x43': implementer_cavium,
'0x50': implementer_ampere,
- '0x51': implementer_qualcomm,
- '0x56': implementer_marvell,
- 'dpaa': implementer_dpaa
+ '0x51': implementer_qualcomm
}
# soc specific aarch64 flags have the highest priority
@@ -202,8 +178,12 @@ soc_generic = {
soc_armada = {
'description': 'Marvell ARMADA',
- 'implementer': '0x56',
+ 'implementer': '0x41',
'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
'numa': false
}
@@ -211,13 +191,23 @@ soc_bluefield = {
'description': 'NVIDIA BlueField',
'implementer': '0x41',
'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
'numa': false
}
soc_dpaa = {
'description': 'NXP DPAA',
- 'implementer': 'dpaa',
+ 'implementer': '0x41',
'part_number': '0xd08',
+ 'flags': [
+ ['RTE_MACHINE', '"dpaa"'],
+ ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false],
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
'numa': false
}
@@ -261,6 +251,10 @@ soc_octeontx2 = {
soc_stingray = {
'description': 'Broadcom Stingray',
'implementer': '0x41',
+ 'flags': [
+ ['RTE_MAX_LCORE', 16],
+ ['RTE_MAX_NUMA_NODES', 1]
+ ],
'part_number': '0xd08',
'numa': false
}