diff mbox series

[V3] config/arm: add Qualcomm Centriq 2400 part number

Message ID 876d348bb6ab493f404c2c1f288262ff3112cada.1623917721.git.thierry.herbelot@6wind.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series [V3] config/arm: add Qualcomm Centriq 2400 part number |

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ci/checkpatch warning coding style issues
ci/iol-intel-Functional success Functional Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-abi-testing success Testing PASS
ci/intel-Testing success Testing PASS
ci/iol-testing success Testing PASS
ci/github-robot success github build: passed
ci/iol-mellanox-Functional fail Functional Testing issues
ci/iol-intel-Performance success Performance Testing PASS

Commit Message

Thierry Herbelot June 17, 2021, 8:16 a.m. UTC 
  0xc00 is for "SoC 2.0" Qualcomm Centriq servers.
0x800 is for "SoC 1.1".

Cc: Jerin Jacob <jerinj@marvell.com>
Cc: Ruifeng Wang <ruifeng.wang@arm.com>
Cc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Cc: Juraj Linkeš <juraj.linkes@pantheon.tech>

Signed-off-by: Thierry Herbelot <thierry.herbelot@6wind.com>
--
V2: add maintainers as Cc
V3: fix meson syntax for the SoC v1.1 machine description
---
 config/arm/meson.build | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

Comments

Ruifeng Wang June 17, 2021, 10:03 a.m. UTC | #1 
> -----Original Message-----
> From: Thierry Herbelot <thierry.herbelot@6wind.com>
> Sent: Thursday, June 17, 2021 4:16 PM
> To: dev@dpdk.org
> Cc: Thierry Herbelot <thierry.herbelot@6wind.com>; thomas@monjalon.net;
> jerinj@marvell.com; Ruifeng Wang <Ruifeng.Wang@arm.com>; Honnappa
> Nagarahalli <Honnappa.Nagarahalli@arm.com>; Juraj Linkeš
> <juraj.linkes@pantheon.tech>
> Subject: [PATCH V3] config/arm: add Qualcomm Centriq 2400 part number
> 
> 0xc00 is for "SoC 2.0" Qualcomm Centriq servers.
> 0x800 is for "SoC 1.1".
> 
> Cc: Jerin Jacob <jerinj@marvell.com>
> Cc: Ruifeng Wang <ruifeng.wang@arm.com>
> Cc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Cc: Juraj Linkeš <juraj.linkes@pantheon.tech>
> 
> Signed-off-by: Thierry Herbelot <thierry.herbelot@6wind.com>
> --
> V2: add maintainers as Cc
> V3: fix meson syntax for the SoC v1.1 machine description
> ---
>  config/arm/meson.build | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> e83a56e0d589..b33303d09023 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -179,7 +179,8 @@ implementer_qualcomm = {
>          ['RTE_MAX_NUMA_NODES', 1]
>      ],
>      'part_number_config': {
> -        '0xc00': {'machine_args':  ['-march=armv8-a+crc']}
> +        '0x800': {'machine_args':  ['-march=armv8-a+crc']},
> +        '0xc00': {'machine_args':  ['-march=armv8-a+crc']},
>      }
>  }
> 
> @@ -223,8 +224,15 @@ soc_bluefield = {
>      'numa': false
>  }
> 
> +soc_centriq2400_v1_1 = {
> +    'description': 'Qualcomm Centriq 2400 (SoC v1.1)',
> +    'implementer': '0x51',
> +    'part_number': '0x800',
> +    'numa': false
> +}
> +
What is the difference between SoC v1.1 and SoC v2.0. Do they have different instruction levels or extensions?
They have the same machine_args. I think the two part numbers can share the same soc_xx. Because cross built binary can run on both SoCs.
What do you think?

Thanks.
>  soc_centriq2400 = {
> -    'description': 'Qualcomm Centriq 2400',
> +    'description': 'Qualcomm Centriq 2400 (SoC v2.0)',
>      'implementer': '0x51',
>      'part_number': '0xc00',
>      'numa': false
> --
> 2.29.2
Thierry Herbelot June 17, 2021, 11:24 a.m. UTC | #2 
On 6/17/21 12:03 PM, Ruifeng Wang wrote:
>> -----Original Message-----
>> From: Thierry Herbelot <thierry.herbelot@6wind.com>
>> Sent: Thursday, June 17, 2021 4:16 PM
>> To: dev@dpdk.org
>> Cc: Thierry Herbelot <thierry.herbelot@6wind.com>; thomas@monjalon.net;
>> jerinj@marvell.com; Ruifeng Wang <Ruifeng.Wang@arm.com>; Honnappa
>> Nagarahalli <Honnappa.Nagarahalli@arm.com>; Juraj Linkeš
>> <juraj.linkes@pantheon.tech>
>> Subject: [PATCH V3] config/arm: add Qualcomm Centriq 2400 part number
>>
>> 0xc00 is for "SoC 2.0" Qualcomm Centriq servers.
>> 0x800 is for "SoC 1.1".
>>
>> Cc: Jerin Jacob <jerinj@marvell.com>
>> Cc: Ruifeng Wang <ruifeng.wang@arm.com>
>> Cc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
>> Cc: Juraj Linkeš <juraj.linkes@pantheon.tech>
>>
>> Signed-off-by: Thierry Herbelot <thierry.herbelot@6wind.com>
>> --
>> V2: add maintainers as Cc
>> V3: fix meson syntax for the SoC v1.1 machine description
>> ---
>>   config/arm/meson.build | 12 ++++++++++--
>>   1 file changed, 10 insertions(+), 2 deletions(-)
>>
>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>> e83a56e0d589..b33303d09023 100644
>> --- a/config/arm/meson.build
>> +++ b/config/arm/meson.build
>> @@ -179,7 +179,8 @@ implementer_qualcomm = {
>>           ['RTE_MAX_NUMA_NODES', 1]
>>       ],
>>       'part_number_config': {
>> -        '0xc00': {'machine_args':  ['-march=armv8-a+crc']}
>> +        '0x800': {'machine_args':  ['-march=armv8-a+crc']},
>> +        '0xc00': {'machine_args':  ['-march=armv8-a+crc']},
>>       }
>>   }
>>
>> @@ -223,8 +224,15 @@ soc_bluefield = {
>>       'numa': false
>>   }
>>
>> +soc_centriq2400_v1_1 = {
>> +    'description': 'Qualcomm Centriq 2400 (SoC v1.1)',
>> +    'implementer': '0x51',
>> +    'part_number': '0x800',
>> +    'numa': false
>> +}
>> +
> What is the difference between SoC v1.1 and SoC v2.0. Do they have different instruction levels or extensions?
> They have the same machine_args. I think the two part numbers can share the same soc_xx. Because cross built binary can run on both SoCs.
> What do you think?

Hello,

There is no visible differences between the two versions.

How do we merge the soc_centriq2400 configurations ?
It would seem it is only possible to have one part_number per soc 
configuration.

	Thierry

> 
> Thanks.
>>   soc_centriq2400 = {
>> -    'description': 'Qualcomm Centriq 2400',
>> +    'description': 'Qualcomm Centriq 2400 (SoC v2.0)',
>>       'implementer': '0x51',
>>       'part_number': '0xc00',
>>       'numa': false
>> --
>> 2.29.2
>
Ruifeng Wang June 17, 2021, 2:46 p.m. UTC | #3 
> -----Original Message-----
> From: Thierry Herbelot <thierry.herbelot@6wind.com>
> Sent: Thursday, June 17, 2021 7:25 PM
> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; dev@dpdk.org
> Cc: thomas@monjalon.net; jerinj@marvell.com; Honnappa Nagarahalli
> <Honnappa.Nagarahalli@arm.com>; Juraj Linkeš
> <juraj.linkes@pantheon.tech>; nd <nd@arm.com>
> Subject: Re: [PATCH V3] config/arm: add Qualcomm Centriq 2400 part
> number
> 
> On 6/17/21 12:03 PM, Ruifeng Wang wrote:
> >> -----Original Message-----
> >> From: Thierry Herbelot <thierry.herbelot@6wind.com>
> >> Sent: Thursday, June 17, 2021 4:16 PM
> >> To: dev@dpdk.org
> >> Cc: Thierry Herbelot <thierry.herbelot@6wind.com>;
> >> thomas@monjalon.net; jerinj@marvell.com; Ruifeng Wang
> >> <Ruifeng.Wang@arm.com>; Honnappa Nagarahalli
> >> <Honnappa.Nagarahalli@arm.com>; Juraj Linkeš
> >> <juraj.linkes@pantheon.tech>
> >> Subject: [PATCH V3] config/arm: add Qualcomm Centriq 2400 part number
> >>
> >> 0xc00 is for "SoC 2.0" Qualcomm Centriq servers.
> >> 0x800 is for "SoC 1.1".
> >>
> >> Cc: Jerin Jacob <jerinj@marvell.com>
> >> Cc: Ruifeng Wang <ruifeng.wang@arm.com>
> >> Cc: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> >> Cc: Juraj Linkeš <juraj.linkes@pantheon.tech>
> >>
> >> Signed-off-by: Thierry Herbelot <thierry.herbelot@6wind.com>
> >> --
> >> V2: add maintainers as Cc
> >> V3: fix meson syntax for the SoC v1.1 machine description
> >> ---
> >>   config/arm/meson.build | 12 ++++++++++--
> >>   1 file changed, 10 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> >> e83a56e0d589..b33303d09023 100644
> >> --- a/config/arm/meson.build
> >> +++ b/config/arm/meson.build
> >> @@ -179,7 +179,8 @@ implementer_qualcomm = {
> >>           ['RTE_MAX_NUMA_NODES', 1]
> >>       ],
> >>       'part_number_config': {
> >> -        '0xc00': {'machine_args':  ['-march=armv8-a+crc']}
> >> +        '0x800': {'machine_args':  ['-march=armv8-a+crc']},
> >> +        '0xc00': {'machine_args':  ['-march=armv8-a+crc']},
> >>       }
> >>   }
> >>
> >> @@ -223,8 +224,15 @@ soc_bluefield = {
> >>       'numa': false
> >>   }
> >>
> >> +soc_centriq2400_v1_1 = {
> >> +    'description': 'Qualcomm Centriq 2400 (SoC v1.1)',
> >> +    'implementer': '0x51',
> >> +    'part_number': '0x800',
> >> +    'numa': false
> >> +}
> >> +
> > What is the difference between SoC v1.1 and SoC v2.0. Do they have
> different instruction levels or extensions?
> > They have the same machine_args. I think the two part numbers can share
> the same soc_xx. Because cross built binary can run on both SoCs.
> > What do you think?
> 
> Hello,
> 
> There is no visible differences between the two versions.
> 
> How do we merge the soc_centriq2400 configurations ?
> It would seem it is only possible to have one part_number per soc
> configuration.
I think we can keep current soc_centriq2400 as there is no visible differences in two versions.
No need to add new part number to soc_centriq2400. It also works for SoC v1.1 when using SoC build.
IMO, only changes in implementer_qualcomm is required. It enables native build on SoC v1.1.

> 
> 	Thierry
> 
> >
> > Thanks.
> >>   soc_centriq2400 = {
> >> -    'description': 'Qualcomm Centriq 2400',
> >> +    'description': 'Qualcomm Centriq 2400 (SoC v2.0)',
> >>       'implementer': '0x51',
> >>       'part_number': '0xc00',
> >>       'numa': false
> >> --
> >> 2.29.2
> >
> 
> --
> Thierry Herbelot
> Senior Software Engineer
> Tel: +33 1 39 30 92 61
> http://www.6wind.com/
> 
> Follow us:
> https://www.linkedin.com/company/6wind/
> https://twitter.com/6WINDsoftware
> https://www.youtube.com/user/6windsoftware
diff mbox series

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index e83a56e0d589..b33303d09023 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -179,7 +179,8 @@  implementer_qualcomm = {
         ['RTE_MAX_NUMA_NODES', 1]
     ],
     'part_number_config': {
-        '0xc00': {'machine_args':  ['-march=armv8-a+crc']}
+        '0x800': {'machine_args':  ['-march=armv8-a+crc']},
+        '0xc00': {'machine_args':  ['-march=armv8-a+crc']},
     }
 }
 
@@ -223,8 +224,15 @@  soc_bluefield = {
     'numa': false
 }
 
+soc_centriq2400_v1_1 = {
+    'description': 'Qualcomm Centriq 2400 (SoC v1.1)',
+    'implementer': '0x51',
+    'part_number': '0x800',
+    'numa': false
+}
+
 soc_centriq2400 = {
-    'description': 'Qualcomm Centriq 2400',
+    'description': 'Qualcomm Centriq 2400 (SoC v2.0)',
     'implementer': '0x51',
     'part_number': '0xc00',
     'numa': false