diff mbox series

net/ice: fix SPI for ESP and NATT not work issue

Message ID 20210712093914.441114-1-simei.su@intel.com (mailing list archive)
State Changes Requested, archived
Delegated to: Qi Zhang
Headers
Series net/ice: fix SPI for ESP and NATT not work issue |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/github-robot success github build: passed
ci/iol-intel-Functional success Functional Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-abi-testing warning Testing issues
ci/intel-Testing success Testing PASS
ci/iol-testing fail Testing issues
ci/iol-intel-Performance fail Performance Testing issues

Commit Message

Simei Su July 12, 2021, 9:39 a.m. UTC 
  This patch fixes this issue by adding the correspongding input set for
ESP and NATT when parsing input set. Also, it adds input set bit for
NAT_T_ESP to distinguish ESP over IP and ESP over UDP.

Fixes: 70feafc1a3f2 ("net/ice: support ESP/NATT flow director to match outer IP")

Signed-off-by: Simei Su <simei.su@intel.com>
---
 drivers/net/ice/ice_fdir_filter.c  | 14 ++++++++++----
 drivers/net/ice/ice_generic_flow.h |  3 +++
 2 files changed, 13 insertions(+), 4 deletions(-)

Comments

Qi Zhang July 13, 2021, 1:07 a.m. UTC | #1 
> -----Original Message-----
> From: Su, Simei <simei.su@intel.com>
> Sent: Monday, July 12, 2021 5:39 PM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>
> Cc: dev@dpdk.org; Cao, Yahui <yahui.cao@intel.com>; Su, Simei
> <simei.su@intel.com>
> Subject: [PATCH] net/ice: fix SPI for ESP and NATT not work issue

What is "ESP and NATT" 
Do you mean 
fix FDIR when SPI as inputset for an ESP over UDP Flow ?

> 
> This patch fixes this issue by adding the correspongding input set for ESP and

s/ correspongding/corresponding

> NATT when parsing input set. Also, it adds input set bit for NAT_T_ESP to
> distinguish ESP over IP and ESP over UDP.
> 
> Fixes: 70feafc1a3f2 ("net/ice: support ESP/NATT flow director to match outer
> IP")
> 
> Signed-off-by: Simei Su <simei.su@intel.com>
> ---
>  drivers/net/ice/ice_fdir_filter.c  | 14 ++++++++++----
> drivers/net/ice/ice_generic_flow.h |  3 +++
>  2 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir_filter.c
> index 4f1aa39..82adb1f 100644
> --- a/drivers/net/ice/ice_fdir_filter.c
> +++ b/drivers/net/ice/ice_fdir_filter.c
> @@ -100,11 +100,11 @@
> 
>  #define ICE_FDIR_INSET_IPV4_NATT_ESP (\
>  	ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \
> -	ICE_INSET_ESP_SPI)
> +	ICE_INSET_NAT_T_ESP_SPI)
> 
>  #define ICE_FDIR_INSET_IPV6_NATT_ESP (\
>  	ICE_INSET_IPV6_SRC | ICE_INSET_IPV6_DST | \
> -	ICE_INSET_ESP_SPI)
> +	ICE_INSET_NAT_T_ESP_SPI)
> 
>  static struct ice_pattern_match_item ice_fdir_pattern_list[] = {
>  	{pattern_ethertype,				ICE_FDIR_INSET_ETH,
> 	ICE_INSET_NONE,			ICE_INSET_NONE},
> @@ -951,6 +951,8 @@ ice_fdir_input_set_parse(uint64_t inset, enum
> ice_flow_field *field)
>  		{ICE_INSET_GTPU_TEID, ICE_FLOW_FIELD_IDX_GTPU_IP_TEID},
>  		{ICE_INSET_GTPU_QFI, ICE_FLOW_FIELD_IDX_GTPU_EH_QFI},
>  		{ICE_INSET_VXLAN_VNI, ICE_FLOW_FIELD_IDX_VXLAN_VNI},
> +		{ICE_INSET_ESP_SPI, ICE_FLOW_FIELD_IDX_ESP_SPI},
> +		{ICE_INSET_NAT_T_ESP_SPI,
> ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI},
>  	};
> 
>  	for (i = 0, j = 0; i < RTE_DIM(ice_inset_map); i++) { @@ -2128,8 +2130,12
> @@ ice_fdir_parse_pattern(__rte_unused struct ice_adapter *ad,
>  			if (!(esp_spec && esp_mask))
>  				break;
> 
> -			if (esp_mask->hdr.spi == UINT32_MAX)
> -				*input_set |= ICE_INSET_ESP_SPI;
> +			if (esp_mask->hdr.spi == UINT32_MAX) {
> +				if (l4 == RTE_FLOW_ITEM_TYPE_UDP)
> +					*input_set |= ICE_INSET_NAT_T_ESP_SPI;
> +				else
> +					*input_set |= ICE_INSET_ESP_SPI;
> +			}
> 
>  			if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
>  				filter->input.ip.v4.sec_parm_idx =
> diff --git a/drivers/net/ice/ice_generic_flow.h
> b/drivers/net/ice/ice_generic_flow.h
> index 0bd38d8..8845a3e 100644
> --- a/drivers/net/ice/ice_generic_flow.h
> +++ b/drivers/net/ice/ice_generic_flow.h
> @@ -26,6 +26,7 @@
>  #define ICE_PROT_AH			BIT_ULL(15)
>  #define ICE_PROT_L2TPV3OIP		BIT_ULL(16)
>  #define ICE_PROT_PFCP			BIT_ULL(17)
> +#define ICE_PROT_NAT_T_ESP		BIT_ULL(18)
> 
>  /* field */
> 
> @@ -117,6 +118,8 @@
>  	(ICE_PROT_PFCP | ICE_PFCP_S_FIELD)
>  #define ICE_INSET_PFCP_SEID \
>  	(ICE_PROT_PFCP | ICE_PFCP_S_FIELD | ICE_PFCP_SEID)
> +#define ICE_INSET_NAT_T_ESP_SPI \
> +	(ICE_PROT_NAT_T_ESP | ICE_ESP_SPI)
> 
>  /* empty pattern */
>  extern enum rte_flow_item_type pattern_empty[];
> --
> 2.9.5
Simei Su July 13, 2021, 1:44 a.m. UTC | #2 
Hi, Qi

> -----Original Message-----
> From: Zhang, Qi Z <qi.z.zhang@intel.com>
> Sent: Tuesday, July 13, 2021 9:07 AM
> To: Su, Simei <simei.su@intel.com>
> Cc: dev@dpdk.org; Cao, Yahui <yahui.cao@intel.com>
> Subject: RE: [PATCH] net/ice: fix SPI for ESP and NATT not work issue
> 
> 
> 
> > -----Original Message-----
> > From: Su, Simei <simei.su@intel.com>
> > Sent: Monday, July 12, 2021 5:39 PM
> > To: Zhang, Qi Z <qi.z.zhang@intel.com>
> > Cc: dev@dpdk.org; Cao, Yahui <yahui.cao@intel.com>; Su, Simei
> > <simei.su@intel.com>
> > Subject: [PATCH] net/ice: fix SPI for ESP and NATT not work issue
> 
> What is "ESP and NATT"
> Do you mean
> fix FDIR when SPI as inputset for an ESP over UDP Flow ?
> 

Yes, I mean when SPI as inputset for both ESP over IP and ESP over UDP.
I will refine the title to let it be more accurate.

> >
> > This patch fixes this issue by adding the correspongding input set for
> > ESP and
> 
> s/ correspongding/corresponding

OK. Thanks for correcting it.

> 
> > NATT when parsing input set. Also, it adds input set bit for NAT_T_ESP
> > to distinguish ESP over IP and ESP over UDP.
> >
> > Fixes: 70feafc1a3f2 ("net/ice: support ESP/NATT flow director to match
> > outer
> > IP")
> >
> > Signed-off-by: Simei Su <simei.su@intel.com>
> > ---
> >  drivers/net/ice/ice_fdir_filter.c  | 14 ++++++++++----
> > drivers/net/ice/ice_generic_flow.h |  3 +++
> >  2 files changed, 13 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/net/ice/ice_fdir_filter.c
> > b/drivers/net/ice/ice_fdir_filter.c
> > index 4f1aa39..82adb1f 100644
> > --- a/drivers/net/ice/ice_fdir_filter.c
> > +++ b/drivers/net/ice/ice_fdir_filter.c
> > @@ -100,11 +100,11 @@
> >
> >  #define ICE_FDIR_INSET_IPV4_NATT_ESP (\  ICE_INSET_IPV4_SRC |
> > ICE_INSET_IPV4_DST | \
> > -ICE_INSET_ESP_SPI)
> > +ICE_INSET_NAT_T_ESP_SPI)
> >
> >  #define ICE_FDIR_INSET_IPV6_NATT_ESP (\  ICE_INSET_IPV6_SRC |
> > ICE_INSET_IPV6_DST | \
> > -ICE_INSET_ESP_SPI)
> > +ICE_INSET_NAT_T_ESP_SPI)
> >
> >  static struct ice_pattern_match_item ice_fdir_pattern_list[] = {
> > {pattern_ethertype,ICE_FDIR_INSET_ETH,
> > ICE_INSET_NONE,ICE_INSET_NONE},
> > @@ -951,6 +951,8 @@ ice_fdir_input_set_parse(uint64_t inset, enum
> > ice_flow_field *field)  {ICE_INSET_GTPU_TEID,
> > ICE_FLOW_FIELD_IDX_GTPU_IP_TEID},  {ICE_INSET_GTPU_QFI,
> > ICE_FLOW_FIELD_IDX_GTPU_EH_QFI},  {ICE_INSET_VXLAN_VNI,
> > ICE_FLOW_FIELD_IDX_VXLAN_VNI},
> > +{ICE_INSET_ESP_SPI, ICE_FLOW_FIELD_IDX_ESP_SPI},
> > +{ICE_INSET_NAT_T_ESP_SPI,
> > ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI},
> >  };
> >
> >  for (i = 0, j = 0; i < RTE_DIM(ice_inset_map); i++) { @@ -2128,8
> > +2130,12 @@ ice_fdir_parse_pattern(__rte_unused struct ice_adapter
> > *ad,  if (!(esp_spec && esp_mask))  break;
> >
> > -if (esp_mask->hdr.spi == UINT32_MAX)
> > -*input_set |= ICE_INSET_ESP_SPI;
> > +if (esp_mask->hdr.spi == UINT32_MAX) { if (l4 ==
> > +RTE_FLOW_ITEM_TYPE_UDP) *input_set |= ICE_INSET_NAT_T_ESP_SPI; else
> > +*input_set |= ICE_INSET_ESP_SPI; }
> >
> >  if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
> >  filter->input.ip.v4.sec_parm_idx =
> > diff --git a/drivers/net/ice/ice_generic_flow.h
> > b/drivers/net/ice/ice_generic_flow.h
> > index 0bd38d8..8845a3e 100644
> > --- a/drivers/net/ice/ice_generic_flow.h
> > +++ b/drivers/net/ice/ice_generic_flow.h
> > @@ -26,6 +26,7 @@
> >  #define ICE_PROT_AHBIT_ULL(15)
> >  #define ICE_PROT_L2TPV3OIPBIT_ULL(16)  #define
> > ICE_PROT_PFCPBIT_ULL(17)
> > +#define ICE_PROT_NAT_T_ESPBIT_ULL(18)
> >
> >  /* field */
> >
> > @@ -117,6 +118,8 @@
> >  (ICE_PROT_PFCP | ICE_PFCP_S_FIELD)
> >  #define ICE_INSET_PFCP_SEID \
> >  (ICE_PROT_PFCP | ICE_PFCP_S_FIELD | ICE_PFCP_SEID)
> > +#define ICE_INSET_NAT_T_ESP_SPI \
> > +(ICE_PROT_NAT_T_ESP | ICE_ESP_SPI)
> >
> >  /* empty pattern */
> >  extern enum rte_flow_item_type pattern_empty[];
> > --
> > 2.9.5
>
diff mbox series

Patch

diff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir_filter.c
index 4f1aa39..82adb1f 100644
--- a/drivers/net/ice/ice_fdir_filter.c
+++ b/drivers/net/ice/ice_fdir_filter.c
@@ -100,11 +100,11 @@ 
 
 #define ICE_FDIR_INSET_IPV4_NATT_ESP (\
 	ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \
-	ICE_INSET_ESP_SPI)
+	ICE_INSET_NAT_T_ESP_SPI)
 
 #define ICE_FDIR_INSET_IPV6_NATT_ESP (\
 	ICE_INSET_IPV6_SRC | ICE_INSET_IPV6_DST | \
-	ICE_INSET_ESP_SPI)
+	ICE_INSET_NAT_T_ESP_SPI)
 
 static struct ice_pattern_match_item ice_fdir_pattern_list[] = {
 	{pattern_ethertype,				ICE_FDIR_INSET_ETH,		ICE_INSET_NONE,			ICE_INSET_NONE},
@@ -951,6 +951,8 @@  ice_fdir_input_set_parse(uint64_t inset, enum ice_flow_field *field)
 		{ICE_INSET_GTPU_TEID, ICE_FLOW_FIELD_IDX_GTPU_IP_TEID},
 		{ICE_INSET_GTPU_QFI, ICE_FLOW_FIELD_IDX_GTPU_EH_QFI},
 		{ICE_INSET_VXLAN_VNI, ICE_FLOW_FIELD_IDX_VXLAN_VNI},
+		{ICE_INSET_ESP_SPI, ICE_FLOW_FIELD_IDX_ESP_SPI},
+		{ICE_INSET_NAT_T_ESP_SPI, ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI},
 	};
 
 	for (i = 0, j = 0; i < RTE_DIM(ice_inset_map); i++) {
@@ -2128,8 +2130,12 @@  ice_fdir_parse_pattern(__rte_unused struct ice_adapter *ad,
 			if (!(esp_spec && esp_mask))
 				break;
 
-			if (esp_mask->hdr.spi == UINT32_MAX)
-				*input_set |= ICE_INSET_ESP_SPI;
+			if (esp_mask->hdr.spi == UINT32_MAX) {
+				if (l4 == RTE_FLOW_ITEM_TYPE_UDP)
+					*input_set |= ICE_INSET_NAT_T_ESP_SPI;
+				else
+					*input_set |= ICE_INSET_ESP_SPI;
+			}
 
 			if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
 				filter->input.ip.v4.sec_parm_idx =
diff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h
index 0bd38d8..8845a3e 100644
--- a/drivers/net/ice/ice_generic_flow.h
+++ b/drivers/net/ice/ice_generic_flow.h
@@ -26,6 +26,7 @@ 
 #define ICE_PROT_AH			BIT_ULL(15)
 #define ICE_PROT_L2TPV3OIP		BIT_ULL(16)
 #define ICE_PROT_PFCP			BIT_ULL(17)
+#define ICE_PROT_NAT_T_ESP		BIT_ULL(18)
 
 /* field */
 
@@ -117,6 +118,8 @@ 
 	(ICE_PROT_PFCP | ICE_PFCP_S_FIELD)
 #define ICE_INSET_PFCP_SEID \
 	(ICE_PROT_PFCP | ICE_PFCP_S_FIELD | ICE_PFCP_SEID)
+#define ICE_INSET_NAT_T_ESP_SPI \
+	(ICE_PROT_NAT_T_ESP | ICE_ESP_SPI)
 
 /* empty pattern */
 extern enum rte_flow_item_type pattern_empty[];