Attachment #73 for bug #361

View | Details | Raw Unified | Return to bug 361
Collapse All | Expand All

Lines 130-139 static bool pci_check_and_mask_intx(struct pci_dev *pdev) Link Here

(-)a/kernel/linux/igb_uio/compat.h (-4 lines)
130	#define HAVE_MSI_LIST_IN_GENERIC_DEVICE 1	130	#define HAVE_MSI_LIST_IN_GENERIC_DEVICE 1
131	#endif	131	#endif
132		132
133	#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 5, 0)
134	#define HAVE_PCI_MSI_MASK_IRQ 1
135	#endif
136
137	#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)	133	#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 8, 0)
138	#define HAVE_ALLOC_IRQ_VECTORS 1	134	#define HAVE_ALLOC_IRQ_VECTORS 1
139	#endif	135	#endif




static int wc_activate;
static char *intr_mode;
static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;

static int
igbuio_pci_enable_interrupts(struct rte_uio_pci_dev *udev);
static void
igbuio_pci_disable_interrupts(struct rte_uio_pci_dev *udev);

/* sriov sysfs */
static ssize_t
show_max_vfs(struct device *dev, struct device_attribute *attr,

	.attrs = dev_attrs,
};

#ifndef HAVE_PCI_MSI_MASK_IRQ
/*
 * It masks the msix on/off of generating MSI-X messages.
 */
static void
igbuio_msix_mask_irq(struct msi_desc *desc, s32 state)
{
	u32 mask_bits = desc->masked;
	unsigned int offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
						PCI_MSIX_ENTRY_VECTOR_CTRL;

	if (state != 0)
		mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
	else
		mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;

	if (mask_bits != desc->masked) {
		writel(mask_bits, desc->mask_base + offset);
		readl(desc->mask_base);
		desc->masked = mask_bits;
	}
}

/*
 * It masks the msi on/off of generating MSI messages.
 */
static void
igbuio_msi_mask_irq(struct pci_dev *pdev, struct msi_desc *desc, int32_t state)
{
	u32 mask_bits = desc->masked;
	u32 offset = desc->irq - pdev->irq;
	u32 mask = 1 << offset;

	if (!desc->msi_attrib.maskbit)
		return;

	if (state != 0)
		mask_bits &= ~mask;
	else
		mask_bits |= mask;

	if (mask_bits != desc->masked) {
		pci_write_config_dword(pdev, desc->mask_pos, mask_bits);
		desc->masked = mask_bits;
	}
}

static void
igbuio_mask_irq(struct pci_dev *pdev, enum rte_intr_mode mode, s32 irq_state)
{
	struct msi_desc *desc;
	struct list_head *msi_list;

#ifdef HAVE_MSI_LIST_IN_GENERIC_DEVICE
	msi_list = &pdev->dev.msi_list;
#else
	msi_list = &pdev->msi_list;
#endif

	if (mode == RTE_INTR_MODE_MSIX) {
		list_for_each_entry(desc, msi_list, list)
			igbuio_msix_mask_irq(desc, irq_state);
	} else if (mode == RTE_INTR_MODE_MSI) {
		list_for_each_entry(desc, msi_list, list)
			igbuio_msi_mask_irq(pdev, desc, irq_state);
	}
}
#endif

/**
 * This is the irqcontrol callback to be registered to uio_info.
 * It can be used to disable/enable interrupt from user space processes.

igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
{
	struct rte_uio_pci_dev *udev = info->priv;
	int err = 0;

#ifdef HAVE_PCI_MSI_MASK_IRQ
	struct irq_data *irq = irq_get_irq_data(udev->info.irq);
#endif

	pci_cfg_access_lock(pdev);

	if (irq_state == 1) {
		if (udev->info.irq <= 0)
			err = igbuio_pci_enable_interrupts(udev);
	} else {
		igbuio_pci_disable_interrupts(udev);
		udev->info.irq = -1;
#else
		igbuio_mask_irq(pdev, udev->mode, irq_state);
#endif
	}

	return err;
		pci_intx(pdev, !!irq_state);

	pci_cfg_access_unlock(pdev);

	return 0;
}

/**

Return to bug 361

Lines 32-37 struct rte_uio_pci_dev { Link Here

(-)a/kernel/linux/igb_uio/igb_uio.c (-91 / +14 lines)
32	static int wc_activate;	32	static int wc_activate;
33	static char *intr_mode;	33	static char *intr_mode;
34	static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;	34	static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
		35
		36	static int
		37	igbuio_pci_enable_interrupts(struct rte_uio_pci_dev *udev);
		38	static void
		39	igbuio_pci_disable_interrupts(struct rte_uio_pci_dev *udev);
		40
35	/* sriov sysfs */	41	/* sriov sysfs */
36	static ssize_t	42	static ssize_t
37	show_max_vfs(struct device dev, struct device_attribute attr,	43	show_max_vfs(struct device dev, struct device_attribute attr,
Lines 72-146 static const struct attribute_group dev_attr_grp = { Link Here
72	.attrs = dev_attrs,	78	.attrs = dev_attrs,
73	};	79	};
74		80
75	#ifndef HAVE_PCI_MSI_MASK_IRQ
76	/*
77	* It masks the msix on/off of generating MSI-X messages.
78	*/
79	static void
80	igbuio_msix_mask_irq(struct msi_desc *desc, s32 state)
81	{
82	u32 mask_bits = desc->masked;
83	unsigned int offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
84	PCI_MSIX_ENTRY_VECTOR_CTRL;
85
86	if (state != 0)
87	mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
88	else
89	mask_bits \|= PCI_MSIX_ENTRY_CTRL_MASKBIT;
90
91	if (mask_bits != desc->masked) {
92	writel(mask_bits, desc->mask_base + offset);
93	readl(desc->mask_base);
94	desc->masked = mask_bits;
95	}
96	}
97
98	/*
99	* It masks the msi on/off of generating MSI messages.
100	*/
101	static void
102	igbuio_msi_mask_irq(struct pci_dev pdev, struct msi_desc desc, int32_t state)
103	{
104	u32 mask_bits = desc->masked;
105	u32 offset = desc->irq - pdev->irq;
106	u32 mask = 1 << offset;
107
108	if (!desc->msi_attrib.maskbit)
109	return;
110
111	if (state != 0)
112	mask_bits &= ~mask;
113	else
114	mask_bits \|= mask;
115
116	if (mask_bits != desc->masked) {
117	pci_write_config_dword(pdev, desc->mask_pos, mask_bits);
118	desc->masked = mask_bits;
119	}
120	}
121
122	static void
123	igbuio_mask_irq(struct pci_dev *pdev, enum rte_intr_mode mode, s32 irq_state)
124	{
125	struct msi_desc *desc;
126	struct list_head *msi_list;
127
128	#ifdef HAVE_MSI_LIST_IN_GENERIC_DEVICE
129	msi_list = &pdev->dev.msi_list;
130	#else
131	msi_list = &pdev->msi_list;
132	#endif
133
134	if (mode == RTE_INTR_MODE_MSIX) {
135	list_for_each_entry(desc, msi_list, list)
136	igbuio_msix_mask_irq(desc, irq_state);
137	} else if (mode == RTE_INTR_MODE_MSI) {
138	list_for_each_entry(desc, msi_list, list)
139	igbuio_msi_mask_irq(pdev, desc, irq_state);
140	}
141	}
142	#endif
143
144	/**	81	/**
145	* This is the irqcontrol callback to be registered to uio_info.	82	* This is the irqcontrol callback to be registered to uio_info.
146	* It can be used to disable/enable interrupt from user space processes.	83	* It can be used to disable/enable interrupt from user space processes.
Lines 158-188 static int Link Here
158	igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)	95	igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
159	{	96	{
160	struct rte_uio_pci_dev *udev = info->priv;	97	struct rte_uio_pci_dev *udev = info->priv;
161	struct pci_dev *pdev = udev->pdev;	98	int err = 0;
162
163	#ifdef HAVE_PCI_MSI_MASK_IRQ
164	struct irq_data *irq = irq_get_irq_data(udev->info.irq);
165	#endif
166
167	pci_cfg_access_lock(pdev);
168		99
169	if (udev->mode == RTE_INTR_MODE_MSIX \|\| udev->mode == RTE_INTR_MODE_MSI) {	100	if (irq_state == 1) {
170	#ifdef HAVE_PCI_MSI_MASK_IRQ	101	if (udev->info.irq <= 0)
171	if (irq_state == 1)	102	err = igbuio_pci_enable_interrupts(udev);
172	pci_msi_unmask_irq(irq);	103	} else {
173	else	104	igbuio_pci_disable_interrupts(udev);
174	pci_msi_mask_irq(irq);	105	udev->info.irq = -1;
175	#else
176	igbuio_mask_irq(pdev, udev->mode, irq_state);
177	#endif
178	}	106	}
179		107
180	if (udev->mode == RTE_INTR_MODE_LEGACY)	108	return err;
181	pci_intx(pdev, !!irq_state);
182
183	pci_cfg_access_unlock(pdev);
184
185	return 0;
186	}	109	}
187		110
188	/**	111	/**