[dts] [dts 1/5] test_plans/nic_single_core_perf_test_plan:update test plan to sync with testcase
lingwei
weix.ling at intel.com
Mon Sep 7 18:49:25 CEST 2020
Signed-off-by: lingwei <weix.ling at intel.com>
---
test_plans/nic_single_core_perf_test_plan.rst | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/test_plans/nic_single_core_perf_test_plan.rst b/test_plans/nic_single_core_perf_test_plan.rst
index 4157c31..9fc5e01 100644
--- a/test_plans/nic_single_core_perf_test_plan.rst
+++ b/test_plans/nic_single_core_perf_test_plan.rst
@@ -62,6 +62,13 @@ Prerequisites
2 TG 25g ports for FVL25G ports
4 TG 10g ports for 4 NNT10G ports
+
+4. Case config::
+ For FVL40g, if test 16 Byte Descriptor, need to set the "CONFIG_RTE_LIBRTE_I40E_16BYTE_RX_DESC=y"
+ in ./config/common_base and re-build DPDK.
+
+ For CVL25G, if test 16 Byte Descriptor, need to set the "CONFIG_RTE_LIBRTE_ICE_16BYTE_RX_DESC=y"
+ in ./config/common_base and re-build DPDK.
Test Case : Single Core Performance Measurement
===============================================
--
2.17.1
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