[dpdk-stable] patch 'examples/ip_pipeline: fix IPv6 endianness' has been queued to stable release 18.08.1

[Kevin Traynor]

Hi,

FYI, your patch has been queued to stable release 18.08.1

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/27/18. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the patch applied
to the branch. If the code is different (ie: not only metadata diffs), due for example to
a change in context or macro names, please double check it.

Thanks.

Kevin Traynor

---
>From d4754ea87c1b542e355726955d3e3eb0b9f0952c Mon Sep 17 00:00:00 2001
From: Reshma Pattan <reshma.pattan at intel.com>
Date: Fri, 28 Sep 2018 17:18:55 +0100
Subject: [PATCH] examples/ip_pipeline: fix IPv6 endianness

[ upstream commit 223be676c3f32d8d8b1bb1d071bb0f151890e6c6 ]

Fix IPv6 endianness from big endian to CPU order.

Fixes: a3a95b7d58 ("examples/ip_pipeline: add table entry commands")

Signed-off-by: Reshma Pattan <reshma.pattan at intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu at intel.com>
---
 examples/ip_pipeline/thread.c | 40 +++++++++++++++++++++--------------
 1 file changed, 24 insertions(+), 16 deletions(-)

diff --git a/examples/ip_pipeline/thread.c b/examples/ip_pipeline/thread.c
index 7fc03332e..b00ea0653 100644
--- a/examples/ip_pipeline/thread.c
+++ b/examples/ip_pipeline/thread.c
@@ -2245,27 +2245,35 @@ match_convert(struct table_rule_match *mh,
 					mh->match.acl.proto_mask;
 
-				ml->acl_add.field_value[1].value.u32 = sa32[0];
+				ml->acl_add.field_value[1].value.u32 =
+					rte_be_to_cpu_32(sa32[0]);
 				ml->acl_add.field_value[1].mask_range.u32 =
 					sa32_depth[0];
-				ml->acl_add.field_value[2].value.u32 = sa32[1];
+				ml->acl_add.field_value[2].value.u32 =
+					rte_be_to_cpu_32(sa32[1]);
 				ml->acl_add.field_value[2].mask_range.u32 =
 					sa32_depth[1];
-				ml->acl_add.field_value[3].value.u32 = sa32[2];
+				ml->acl_add.field_value[3].value.u32 =
+					rte_be_to_cpu_32(sa32[2]);
 				ml->acl_add.field_value[3].mask_range.u32 =
 					sa32_depth[2];
-				ml->acl_add.field_value[4].value.u32 = sa32[3];
+				ml->acl_add.field_value[4].value.u32 =
+					rte_be_to_cpu_32(sa32[3]);
 				ml->acl_add.field_value[4].mask_range.u32 =
 					sa32_depth[3];
 
-				ml->acl_add.field_value[5].value.u32 = da32[0];
+				ml->acl_add.field_value[5].value.u32 =
+					rte_be_to_cpu_32(da32[0]);
 				ml->acl_add.field_value[5].mask_range.u32 =
 					da32_depth[0];
-				ml->acl_add.field_value[6].value.u32 = da32[1];
+				ml->acl_add.field_value[6].value.u32 =
+					rte_be_to_cpu_32(da32[1]);
 				ml->acl_add.field_value[6].mask_range.u32 =
 					da32_depth[1];
-				ml->acl_add.field_value[7].value.u32 = da32[2];
+				ml->acl_add.field_value[7].value.u32 =
+					rte_be_to_cpu_32(da32[2]);
 				ml->acl_add.field_value[7].mask_range.u32 =
 					da32_depth[2];
-				ml->acl_add.field_value[8].value.u32 = da32[3];
+				ml->acl_add.field_value[8].value.u32 =
+					rte_be_to_cpu_32(da32[3]);
 				ml->acl_add.field_value[8].mask_range.u32 =
 					da32_depth[3];
@@ -2309,34 +2317,34 @@ match_convert(struct table_rule_match *mh,
 
 				ml->acl_delete.field_value[1].value.u32 =
-					sa32[0];
+					rte_be_to_cpu_32(sa32[0]);
 				ml->acl_delete.field_value[1].mask_range.u32 =
 					sa32_depth[0];
 				ml->acl_delete.field_value[2].value.u32 =
-					sa32[1];
+					rte_be_to_cpu_32(sa32[1]);
 				ml->acl_delete.field_value[2].mask_range.u32 =
 					sa32_depth[1];
 				ml->acl_delete.field_value[3].value.u32 =
-					sa32[2];
+					rte_be_to_cpu_32(sa32[2]);
 				ml->acl_delete.field_value[3].mask_range.u32 =
 					sa32_depth[2];
 				ml->acl_delete.field_value[4].value.u32 =
-					sa32[3];
+					rte_be_to_cpu_32(sa32[3]);
 				ml->acl_delete.field_value[4].mask_range.u32 =
 					sa32_depth[3];
 
 				ml->acl_delete.field_value[5].value.u32 =
-					da32[0];
+					rte_be_to_cpu_32(da32[0]);
 				ml->acl_delete.field_value[5].mask_range.u32 =
 					da32_depth[0];
 				ml->acl_delete.field_value[6].value.u32 =
-					da32[1];
+					rte_be_to_cpu_32(da32[1]);
 				ml->acl_delete.field_value[6].mask_range.u32 =
 					da32_depth[1];
 				ml->acl_delete.field_value[7].value.u32 =
-					da32[2];
+					rte_be_to_cpu_32(da32[2]);
 				ml->acl_delete.field_value[7].mask_range.u32 =
 					da32_depth[2];
 				ml->acl_delete.field_value[8].value.u32 =
-					da32[3];
+					rte_be_to_cpu_32(da32[3]);
 				ml->acl_delete.field_value[8].mask_range.u32 =
 					da32_depth[3];
-- 
2.19.0

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2018-11-21 16:44:32.839510153 +0000
+++ 0070-examples-ip_pipeline-fix-IPv6-endianness.patch	2018-11-21 16:44:30.000000000 +0000
@@ -1,12 +1,13 @@
-From 223be676c3f32d8d8b1bb1d071bb0f151890e6c6 Mon Sep 17 00:00:00 2001
+From d4754ea87c1b542e355726955d3e3eb0b9f0952c Mon Sep 17 00:00:00 2001
 From: Reshma Pattan <reshma.pattan at intel.com>
 Date: Fri, 28 Sep 2018 17:18:55 +0100
 Subject: [PATCH] examples/ip_pipeline: fix IPv6 endianness
 
+[ upstream commit 223be676c3f32d8d8b1bb1d071bb0f151890e6c6 ]
+
 Fix IPv6 endianness from big endian to CPU order.
 
 Fixes: a3a95b7d58 ("examples/ip_pipeline: add table entry commands")
-Cc: stable at dpdk.org
 
 Signed-off-by: Reshma Pattan <reshma.pattan at intel.com>
 Acked-by: Cristian Dumitrescu <cristian.dumitrescu at intel.com>
@@ -15,7 +16,7 @@
  1 file changed, 24 insertions(+), 16 deletions(-)
 
 diff --git a/examples/ip_pipeline/thread.c b/examples/ip_pipeline/thread.c
-index ca741952a..3ec44c9a9 100644
+index 7fc03332e..b00ea0653 100644
 --- a/examples/ip_pipeline/thread.c
 +++ b/examples/ip_pipeline/thread.c
 @@ -2245,27 +2245,35 @@ match_convert(struct table_rule_match *mh,