[dpdk-stable] patch 'net/softnic: fix IPv6 endianness' has been queued to stable release 18.08.1
Kevin Traynor
ktraynor at redhat.com
Wed Nov 21 17:48:25 CET 2018
Hi,
FYI, your patch has been queued to stable release 18.08.1
Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/27/18. So please
shout if anyone has objections.
Also note that after the patch there's a diff of the upstream commit vs the patch applied
to the branch. If the code is different (ie: not only metadata diffs), due for example to
a change in context or macro names, please double check it.
Thanks.
Kevin Traynor
---
>From 14a4ec3232447a48bd4cec06cffcc70111cda859 Mon Sep 17 00:00:00 2001
From: Reshma Pattan <reshma.pattan at intel.com>
Date: Fri, 28 Sep 2018 17:18:54 +0100
Subject: [PATCH] net/softnic: fix IPv6 endianness
[ upstream commit 13b8c6802d456b3acd9b5cf47abb60594f892e9b ]
Fix IPv6 endianness from big endian to CPU order.
Fixes: ee19326a4b ("net/softnic: add command for pipeline table entries")
Signed-off-by: Reshma Pattan <reshma.pattan at intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu at intel.com>
---
drivers/net/softnic/rte_eth_softnic_thread.c | 40 ++++++++++++--------
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/drivers/net/softnic/rte_eth_softnic_thread.c b/drivers/net/softnic/rte_eth_softnic_thread.c
index 8a1509030..2be81900a 100644
--- a/drivers/net/softnic/rte_eth_softnic_thread.c
+++ b/drivers/net/softnic/rte_eth_softnic_thread.c
@@ -2203,27 +2203,35 @@ match_convert(struct softnic_table_rule_match *mh,
mh->match.acl.proto_mask;
- ml->acl_add.field_value[1].value.u32 = sa32[0];
+ ml->acl_add.field_value[1].value.u32 =
+ rte_be_to_cpu_32(sa32[0]);
ml->acl_add.field_value[1].mask_range.u32 =
sa32_depth[0];
- ml->acl_add.field_value[2].value.u32 = sa32[1];
+ ml->acl_add.field_value[2].value.u32 =
+ rte_be_to_cpu_32(sa32[1]);
ml->acl_add.field_value[2].mask_range.u32 =
sa32_depth[1];
- ml->acl_add.field_value[3].value.u32 = sa32[2];
+ ml->acl_add.field_value[3].value.u32 =
+ rte_be_to_cpu_32(sa32[2]);
ml->acl_add.field_value[3].mask_range.u32 =
sa32_depth[2];
- ml->acl_add.field_value[4].value.u32 = sa32[3];
+ ml->acl_add.field_value[4].value.u32 =
+ rte_be_to_cpu_32(sa32[3]);
ml->acl_add.field_value[4].mask_range.u32 =
sa32_depth[3];
- ml->acl_add.field_value[5].value.u32 = da32[0];
+ ml->acl_add.field_value[5].value.u32 =
+ rte_be_to_cpu_32(da32[0]);
ml->acl_add.field_value[5].mask_range.u32 =
da32_depth[0];
- ml->acl_add.field_value[6].value.u32 = da32[1];
+ ml->acl_add.field_value[6].value.u32 =
+ rte_be_to_cpu_32(da32[1]);
ml->acl_add.field_value[6].mask_range.u32 =
da32_depth[1];
- ml->acl_add.field_value[7].value.u32 = da32[2];
+ ml->acl_add.field_value[7].value.u32 =
+ rte_be_to_cpu_32(da32[2]);
ml->acl_add.field_value[7].mask_range.u32 =
da32_depth[2];
- ml->acl_add.field_value[8].value.u32 = da32[3];
+ ml->acl_add.field_value[8].value.u32 =
+ rte_be_to_cpu_32(da32[3]);
ml->acl_add.field_value[8].mask_range.u32 =
da32_depth[3];
@@ -2265,34 +2273,34 @@ match_convert(struct softnic_table_rule_match *mh,
ml->acl_delete.field_value[1].value.u32 =
- sa32[0];
+ rte_be_to_cpu_32(sa32[0]);
ml->acl_delete.field_value[1].mask_range.u32 =
sa32_depth[0];
ml->acl_delete.field_value[2].value.u32 =
- sa32[1];
+ rte_be_to_cpu_32(sa32[1]);
ml->acl_delete.field_value[2].mask_range.u32 =
sa32_depth[1];
ml->acl_delete.field_value[3].value.u32 =
- sa32[2];
+ rte_be_to_cpu_32(sa32[2]);
ml->acl_delete.field_value[3].mask_range.u32 =
sa32_depth[2];
ml->acl_delete.field_value[4].value.u32 =
- sa32[3];
+ rte_be_to_cpu_32(sa32[3]);
ml->acl_delete.field_value[4].mask_range.u32 =
sa32_depth[3];
ml->acl_delete.field_value[5].value.u32 =
- da32[0];
+ rte_be_to_cpu_32(da32[0]);
ml->acl_delete.field_value[5].mask_range.u32 =
da32_depth[0];
ml->acl_delete.field_value[6].value.u32 =
- da32[1];
+ rte_be_to_cpu_32(da32[1]);
ml->acl_delete.field_value[6].mask_range.u32 =
da32_depth[1];
ml->acl_delete.field_value[7].value.u32 =
- da32[2];
+ rte_be_to_cpu_32(da32[2]);
ml->acl_delete.field_value[7].mask_range.u32 =
da32_depth[2];
ml->acl_delete.field_value[8].value.u32 =
- da32[3];
+ rte_be_to_cpu_32(da32[3]);
ml->acl_delete.field_value[8].mask_range.u32 =
da32_depth[3];
--
2.19.0
---
Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- - 2018-11-21 16:44:32.865606447 +0000
+++ 0071-net-softnic-fix-IPv6-endianness.patch 2018-11-21 16:44:30.000000000 +0000
@@ -1,12 +1,13 @@
-From 13b8c6802d456b3acd9b5cf47abb60594f892e9b Mon Sep 17 00:00:00 2001
+From 14a4ec3232447a48bd4cec06cffcc70111cda859 Mon Sep 17 00:00:00 2001
From: Reshma Pattan <reshma.pattan at intel.com>
Date: Fri, 28 Sep 2018 17:18:54 +0100
Subject: [PATCH] net/softnic: fix IPv6 endianness
+[ upstream commit 13b8c6802d456b3acd9b5cf47abb60594f892e9b ]
+
Fix IPv6 endianness from big endian to CPU order.
Fixes: ee19326a4b ("net/softnic: add command for pipeline table entries")
-Cc: stable at dpdk.org
Signed-off-by: Reshma Pattan <reshma.pattan at intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu at intel.com>
@@ -15,10 +16,10 @@
1 file changed, 24 insertions(+), 16 deletions(-)
diff --git a/drivers/net/softnic/rte_eth_softnic_thread.c b/drivers/net/softnic/rte_eth_softnic_thread.c
-index 76217fcde..87b5592b0 100644
+index 8a1509030..2be81900a 100644
--- a/drivers/net/softnic/rte_eth_softnic_thread.c
+++ b/drivers/net/softnic/rte_eth_softnic_thread.c
-@@ -2241,27 +2241,35 @@ match_convert(struct softnic_table_rule_match *mh,
+@@ -2203,27 +2203,35 @@ match_convert(struct softnic_table_rule_match *mh,
mh->match.acl.proto_mask;
- ml->acl_add.field_value[1].value.u32 = sa32[0];
@@ -62,7 +63,7 @@
+ rte_be_to_cpu_32(da32[3]);
ml->acl_add.field_value[8].mask_range.u32 =
da32_depth[3];
-@@ -2303,34 +2311,34 @@ match_convert(struct softnic_table_rule_match *mh,
+@@ -2265,34 +2273,34 @@ match_convert(struct softnic_table_rule_match *mh,
ml->acl_delete.field_value[1].value.u32 =
- sa32[0];
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