[dpdk-stable] patch 'net/mlx5: fix software parsing support query' has been queued to stable release 20.11.4

Xueming Li xuemingl at nvidia.com
Wed Nov 10 07:30:33 CET 2021

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Hi,

FYI, your patch has been queued to stable release 20.11.4

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/12/21. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/steevenlee/dpdk

This queued commit can be viewed at:
https://github.com/steevenlee/dpdk/commit/29a18f0f26e6d9597d415dba9d9b6f7960d23237

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 29a18f0f26e6d9597d415dba9d9b6f7960d23237 Mon Sep 17 00:00:00 2001
From: Tal Shnaiderman <talshn at nvidia.com>
Date: Tue, 12 Oct 2021 15:45:42 +0300
Subject: [PATCH] net/mlx5: fix software parsing support query
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit accf3cfce4cb531bb1d5aceb1c1c84cc36ae9175 ]

Currently, the PMD decides if the software parsing
offload can enable outer IPv4 checksum and tunneled
TSO support by checking config->hw_csum and config->tso
respectively.

This is incorrect, the right way is to check the following
flags returned by the mlx5dv_query_device function:

MLX5DV_SW_PARSING - check general swp support.
MLX5DV_SW_PARSING_CSUM - check swp checksum support.
MLX5DV_SW_PARSING_LSO - check swp LSO/TSO support.

The fix enables the offloads according to the correct
flags returned by the kernel.

Fixes: e46821e9fcdc ("net/mlx5: separate generic tunnel TSO from the standard one")

Signed-off-by: Tal Shnaiderman <talshn at nvidia.com>
Acked-by: Matan Azrad <matan at nvidia.com>
Tested-by: Idan Hackmon <idanhac at nvidia.com>
---
 drivers/net/mlx5/linux/mlx5_os.c |  3 ++-
 drivers/net/mlx5/linux/mlx5_os.h | 12 ++++++++++++
 drivers/net/mlx5/mlx5.h          |  2 +-
 drivers/net/mlx5/mlx5_txq.c      | 15 +++++++++------
 4 files changed, 24 insertions(+), 8 deletions(-)

diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 04700fcbeb..714feba36e 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -916,7 +916,8 @@ err_secondary:
 		swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
 	DRV_LOG(DEBUG, "SWP support: %u", swp);
 #endif
-	config->swp = !!swp;
+	config->swp = swp & (MLX5_SW_PARSING_CAP | MLX5_SW_PARSING_CSUM_CAP |
+		MLX5_SW_PARSING_TSO_CAP);
 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
 	if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
 		struct mlx5dv_striding_rq_caps mprq_caps =
diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h
index 7dbacceabe..d9d464b5e3 100644
--- a/drivers/net/mlx5/linux/mlx5_os.h
+++ b/drivers/net/mlx5/linux/mlx5_os.h
@@ -19,4 +19,16 @@ enum {
 #define PCI_DRV_FLAGS  (RTE_PCI_DRV_INTR_LSC | \
 			RTE_PCI_DRV_INTR_RMV | \
 			RTE_PCI_DRV_PROBE_AGAIN)
+
+enum mlx5_sw_parsing_offloads {
+#ifdef HAVE_IBV_MLX5_MOD_SWP
+	MLX5_SW_PARSING_CAP      = MLX5DV_SW_PARSING,
+	MLX5_SW_PARSING_CSUM_CAP = MLX5DV_SW_PARSING_CSUM,
+	MLX5_SW_PARSING_TSO_CAP  = MLX5DV_SW_PARSING_LSO,
+#else
+	MLX5_SW_PARSING_CAP      = 0,
+	MLX5_SW_PARSING_CSUM_CAP = 0,
+	MLX5_SW_PARSING_TSO_CAP  = 0,
+#endif
+};
 #endif /* RTE_PMD_MLX5_OS_H_ */
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 69eda27a0f..9c8991aba6 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -218,7 +218,7 @@ struct mlx5_dev_config {
 	unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
 	unsigned int lacp_by_user:1;
 	/* Enable user to manage LACP traffic. */
-	unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
+	unsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */
 	unsigned int devx:1; /* Whether devx interface is available or not. */
 	unsigned int dest_tir:1; /* Whether advanced DR API is available. */
 	unsigned int reclaim_mode:2; /* Memory reclaim mode. */
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 9ec7b57f1c..1354cc9619 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -109,9 +109,9 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
 	if (config->tx_pp)
 		offloads |= DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP;
 	if (config->swp) {
-		if (config->hw_csum)
+		if (config->swp & MLX5_SW_PARSING_CSUM_CAP)
 			offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
-		if (config->tso)
+		if (config->swp & MLX5_SW_PARSING_TSO_CAP)
 			offloads |= (DEV_TX_OFFLOAD_IP_TNL_TSO |
 				     DEV_TX_OFFLOAD_UDP_TNL_TSO);
 	}
@@ -971,10 +971,13 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
 		txq_ctrl->txq.tso_en = 1;
 	}
 	txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
-	txq_ctrl->txq.swp_en = ((DEV_TX_OFFLOAD_IP_TNL_TSO |
-				 DEV_TX_OFFLOAD_UDP_TNL_TSO |
-				 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) &
-				txq_ctrl->txq.offloads) && config->swp;
+	txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |
+				  DEV_TX_OFFLOAD_UDP_TNL_TSO) &
+				  txq_ctrl->txq.offloads) && (config->swp &
+				  MLX5_SW_PARSING_TSO_CAP)) |
+				((DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM &
+				 txq_ctrl->txq.offloads) && (config->swp &
+				 MLX5_SW_PARSING_CSUM_CAP));
 }
 
 /**
-- 
2.33.0

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2021-11-10 14:17:08.562122974 +0800
+++ 0149-net-mlx5-fix-software-parsing-support-query.patch	2021-11-10 14:17:01.937412212 +0800
@@ -1 +1 @@
-From accf3cfce4cb531bb1d5aceb1c1c84cc36ae9175 Mon Sep 17 00:00:00 2001
+From 29a18f0f26e6d9597d415dba9d9b6f7960d23237 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit accf3cfce4cb531bb1d5aceb1c1c84cc36ae9175 ]
@@ -22 +24,0 @@
-Cc: stable at dpdk.org
@@ -35 +37 @@
-index 0dcf5000e9..e08082ed70 100644
+index 04700fcbeb..714feba36e 100644
@@ -38 +40 @@
-@@ -1111,7 +1111,8 @@ err_secondary:
+@@ -916,7 +916,8 @@ err_secondary:
@@ -49 +51 @@
-index 2991d37df2..da036edb72 100644
+index 7dbacceabe..d9d464b5e3 100644
@@ -52,4 +54,4 @@
-@@ -21,4 +21,16 @@ enum {
- 
- int mlx5_auxiliary_get_ifindex(const char *sf_name);
- 
+@@ -19,4 +19,16 @@ enum {
+ #define PCI_DRV_FLAGS  (RTE_PCI_DRV_INTR_LSC | \
+ 			RTE_PCI_DRV_INTR_RMV | \
+ 			RTE_PCI_DRV_PROBE_AGAIN)
@@ -70 +72 @@
-index 6811b8bd35..d74ac19cf8 100644
+index 69eda27a0f..9c8991aba6 100644
@@ -73 +75 @@
-@@ -267,7 +267,7 @@ struct mlx5_dev_config {
+@@ -218,7 +218,7 @@ struct mlx5_dev_config {
@@ -83 +85 @@
-index 92fbdab568..eb26367827 100644
+index 9ec7b57f1c..1354cc9619 100644
@@ -86 +88 @@
-@@ -111,9 +111,9 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
+@@ -109,9 +109,9 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
@@ -98 +100 @@
-@@ -972,10 +972,13 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
+@@ -971,10 +971,13 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)

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