[dpdk-stable] patch 'net/mlx5: fix tunneling support query' has been queued to stable release 20.11.4

Xueming Li xuemingl at nvidia.com
Wed Nov 10 07:30:34 CET 2021
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Hi,

FYI, your patch has been queued to stable release 20.11.4

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 11/12/21. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/steevenlee/dpdk

This queued commit can be viewed at:
https://github.com/steevenlee/dpdk/commit/3d8dfe94bdc766526f3d61b8900e8d7fd6a06ede

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 3d8dfe94bdc766526f3d61b8900e8d7fd6a06ede Mon Sep 17 00:00:00 2001
From: Tal Shnaiderman <talshn at nvidia.com>
Date: Tue, 12 Oct 2021 15:45:45 +0300
Subject: [PATCH] net/mlx5: fix tunneling support query
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit c1a320bf899e5ff8d3e3a4f291ee61c8a98a8bda ]

Currently, the PMD decides if the tunneling offload
can enable VXLAN/GRE/GENEVE tunneled TSO support by checking
config->tunnel_en (single bit) and config->tso.

This is incorrect, the right way is to check the following
flags returned by the mlx5dv_query_device function:

MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN - if supported the offload
DEV_TX_OFFLOAD_VXLAN_TNL_TSO can be enabled.
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE - if supported the offload
DEV_TX_OFFLOAD_GRE_TNL_TSO can be enabled.
MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE - if supported the offload
DEV_TX_OFFLOAD_GENEVE_TNL_TSO can be enabled.

The fix enables the offloads according to the correct
flags returned by the kernel.

Fixes: dbccb4cddcd2 ("net/mlx5: convert to new Tx offloads API")

Signed-off-by: Tal Shnaiderman <talshn at nvidia.com>
Acked-by: Matan Azrad <matan at nvidia.com>
Tested-by: Idan Hackmon <idanhac at nvidia.com>
---
 drivers/net/mlx5/linux/mlx5_os.c | 28 +++++++++++++++++-----------
 drivers/net/mlx5/linux/mlx5_os.h | 15 +++++++++++++++
 drivers/net/mlx5/mlx5.h          |  2 +-
 drivers/net/mlx5/mlx5_txq.c      | 24 +++++++++++++++++++-----
 4 files changed, 52 insertions(+), 17 deletions(-)

diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c
index 714feba36e..cc4fa3dd97 100644
--- a/drivers/net/mlx5/linux/mlx5_os.c
+++ b/drivers/net/mlx5/linux/mlx5_os.c
@@ -755,7 +755,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
 	int err = 0;
 	unsigned int hw_padding = 0;
 	unsigned int mps;
-	unsigned int tunnel_en = 0;
 	unsigned int mpls_en = 0;
 	unsigned int swp = 0;
 	unsigned int mprq = 0;
@@ -949,20 +948,27 @@ err_secondary:
 	config->cqe_comp = 1;
 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
 	if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
-		tunnel_en = ((dv_attr.tunnel_offloads_caps &
-			      MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
-			     (dv_attr.tunnel_offloads_caps &
-			      MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
-			     (dv_attr.tunnel_offloads_caps &
-			      MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
-	}
-	DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
-		tunnel_en ? "" : "not ");
+		config->tunnel_en = dv_attr.tunnel_offloads_caps &
+			     (MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN |
+			      MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE |
+			      MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE);
+	}
+	if (config->tunnel_en) {
+		DRV_LOG(DEBUG, "tunnel offloading is supported for %s%s%s",
+		config->tunnel_en &
+		MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN ? "[VXLAN]" : "",
+		config->tunnel_en &
+		MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE ? "[GRE]" : "",
+		config->tunnel_en &
+		MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE ? "[GENEVE]" : ""
+		);
+	} else {
+		DRV_LOG(DEBUG, "tunnel offloading is not supported");
+	}
 #else
 	DRV_LOG(WARNING,
 		"tunnel offloading disabled due to old OFED/rdma-core version");
 #endif
-	config->tunnel_en = tunnel_en;
 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
 	mpls_en = ((dv_attr.tunnel_offloads_caps &
 		    MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
diff --git a/drivers/net/mlx5/linux/mlx5_os.h b/drivers/net/mlx5/linux/mlx5_os.h
index d9d464b5e3..a524f71d2b 100644
--- a/drivers/net/mlx5/linux/mlx5_os.h
+++ b/drivers/net/mlx5/linux/mlx5_os.h
@@ -31,4 +31,19 @@ enum mlx5_sw_parsing_offloads {
 	MLX5_SW_PARSING_TSO_CAP  = 0,
 #endif
 };
+
+enum mlx5_tunnel_offloads {
+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
+	MLX5_TUNNELED_OFFLOADS_VXLAN_CAP  =
+		MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN,
+	MLX5_TUNNELED_OFFLOADS_GRE_CAP    =
+		MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE,
+	MLX5_TUNNELED_OFFLOADS_GENEVE_CAP =
+		MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE,
+#else
+	MLX5_TUNNELED_OFFLOADS_VXLAN_CAP  = 0,
+	MLX5_TUNNELED_OFFLOADS_GRE_CAP	  = 0,
+	MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 0,
+#endif
+};
 #endif /* RTE_PMD_MLX5_OS_H_ */
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 9c8991aba6..3d6d5bb923 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -202,7 +202,7 @@ struct mlx5_dev_config {
 	unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
 	unsigned int hw_padding:1; /* End alignment padding is supported. */
 	unsigned int vf:1; /* This is a VF. */
-	unsigned int tunnel_en:1;
+	unsigned int tunnel_en:3;
 	/* Whether tunnel stateless offloads are supported. */
 	unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
 	unsigned int cqe_comp:1; /* CQE compression is enabled. */
diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c
index 1354cc9619..5f1a179df3 100644
--- a/drivers/net/mlx5/mlx5_txq.c
+++ b/drivers/net/mlx5/mlx5_txq.c
@@ -118,10 +118,17 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
 	if (config->tunnel_en) {
 		if (config->hw_csum)
 			offloads |= DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
-		if (config->tso)
-			offloads |= (DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
-				     DEV_TX_OFFLOAD_GRE_TNL_TSO |
-				     DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
+		if (config->tso) {
+			if (config->tunnel_en &
+				MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)
+				offloads |= DEV_TX_OFFLOAD_VXLAN_TNL_TSO;
+			if (config->tunnel_en &
+				MLX5_TUNNELED_OFFLOADS_GRE_CAP)
+				offloads |= DEV_TX_OFFLOAD_GRE_TNL_TSO;
+			if (config->tunnel_en &
+				MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)
+				offloads |= DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
+		}
 	}
 	return offloads;
 }
@@ -970,7 +977,14 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
 						    MLX5_MAX_TSO_HEADER);
 		txq_ctrl->txq.tso_en = 1;
 	}
-	txq_ctrl->txq.tunnel_en = config->tunnel_en | config->swp;
+	if (((DEV_TX_OFFLOAD_VXLAN_TNL_TSO & txq_ctrl->txq.offloads) &&
+	    (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_VXLAN_CAP)) |
+	   ((DEV_TX_OFFLOAD_GRE_TNL_TSO & txq_ctrl->txq.offloads) &&
+	    (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GRE_CAP)) |
+	   ((DEV_TX_OFFLOAD_GENEVE_TNL_TSO & txq_ctrl->txq.offloads) &&
+	    (config->tunnel_en & MLX5_TUNNELED_OFFLOADS_GENEVE_CAP)) |
+	   (config->swp  & MLX5_SW_PARSING_TSO_CAP))
+		txq_ctrl->txq.tunnel_en = 1;
 	txq_ctrl->txq.swp_en = (((DEV_TX_OFFLOAD_IP_TNL_TSO |
 				  DEV_TX_OFFLOAD_UDP_TNL_TSO) &
 				  txq_ctrl->txq.offloads) && (config->swp &
-- 
2.33.0

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2021-11-10 14:17:08.606458859 +0800
+++ 0150-net-mlx5-fix-tunneling-support-query.patch	2021-11-10 14:17:01.937412212 +0800
@@ -1 +1 @@
-From c1a320bf899e5ff8d3e3a4f291ee61c8a98a8bda Mon Sep 17 00:00:00 2001
+From 3d8dfe94bdc766526f3d61b8900e8d7fd6a06ede Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit c1a320bf899e5ff8d3e3a4f291ee61c8a98a8bda ]
@@ -24 +26,0 @@
-Cc: stable at dpdk.org
@@ -30,6 +32,5 @@
- drivers/net/mlx5/linux/mlx5_os.c   | 28 +++++++++++++++++-----------
- drivers/net/mlx5/linux/mlx5_os.h   | 15 +++++++++++++++
- drivers/net/mlx5/mlx5.h            |  2 +-
- drivers/net/mlx5/mlx5_txq.c        | 24 +++++++++++++++++++-----
- drivers/net/mlx5/windows/mlx5_os.h |  6 ++++++
- 5 files changed, 58 insertions(+), 17 deletions(-)
+ drivers/net/mlx5/linux/mlx5_os.c | 28 +++++++++++++++++-----------
+ drivers/net/mlx5/linux/mlx5_os.h | 15 +++++++++++++++
+ drivers/net/mlx5/mlx5.h          |  2 +-
+ drivers/net/mlx5/mlx5_txq.c      | 24 +++++++++++++++++++-----
+ 4 files changed, 52 insertions(+), 17 deletions(-)
@@ -38 +39 @@
-index e08082ed70..26a8d75b99 100644
+index 714feba36e..cc4fa3dd97 100644
@@ -41 +42 @@
-@@ -963,7 +963,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
+@@ -755,7 +755,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
@@ -49 +50 @@
-@@ -1144,20 +1143,27 @@ err_secondary:
+@@ -949,20 +948,27 @@ err_secondary:
@@ -88 +89 @@
-index da036edb72..80c70d713a 100644
+index d9d464b5e3..a524f71d2b 100644
@@ -91 +92 @@
-@@ -33,4 +33,19 @@ enum mlx5_sw_parsing_offloads {
+@@ -31,4 +31,19 @@ enum mlx5_sw_parsing_offloads {
@@ -112 +113 @@
-index 483bf35f85..6dde6210d1 100644
+index 9c8991aba6..3d6d5bb923 100644
@@ -115 +116,2 @@
-@@ -251,7 +251,7 @@ struct mlx5_dev_config {
+@@ -202,7 +202,7 @@ struct mlx5_dev_config {
+ 	unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
@@ -118 +119,0 @@
- 	unsigned int sf:1; /* This is a SF. */
@@ -125 +126 @@
-index eb26367827..1f92250f5e 100644
+index 1354cc9619..5f1a179df3 100644
@@ -128 +129 @@
-@@ -120,10 +120,17 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
+@@ -118,10 +118,17 @@ mlx5_get_tx_port_offloads(struct rte_eth_dev *dev)
@@ -148,3 +149,3 @@
- 	if (!config->mprq.enabled)
- 		offloads |= DEV_TX_OFFLOAD_MBUF_FAST_FREE;
-@@ -971,7 +978,14 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
+ 	return offloads;
+ }
+@@ -970,7 +977,14 @@ txq_set_params(struct mlx5_txq_ctrl *txq_ctrl)
@@ -166,15 +166,0 @@
-diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h
-index 6de683357c..8b58265687 100644
---- a/drivers/net/mlx5/windows/mlx5_os.h
-+++ b/drivers/net/mlx5/windows/mlx5_os.h
-@@ -22,4 +22,10 @@ enum mlx5_sw_parsing_offloads {
- 	MLX5_SW_PARSING_TSO_CAP =  1 << 2,
- };
- 
-+enum mlx5_tunnel_offloads {
-+	MLX5_TUNNELED_OFFLOADS_VXLAN_CAP  = 1 << 0,
-+	MLX5_TUNNELED_OFFLOADS_GRE_CAP	  = 1 << 1,
-+	MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 1 << 2,
-+};
-+
- #endif /* RTE_PMD_MLX5_OS_H_ */
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