patch 'net/iavf: fix Rx queue interrupt setting' has been queued to stable release 20.11.6

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 20.11.6

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 06/23/22. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/steevenlee/dpdk

This queued commit can be viewed at:
https://github.com/steevenlee/dpdk/commit/789223ef41ebf4a8b9efecf516cb415f2bf48cf0

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 789223ef41ebf4a8b9efecf516cb415f2bf48cf0 Mon Sep 17 00:00:00 2001
From: Ke Zhang <ke1x.zhang at intel.com>
Date: Fri, 20 May 2022 03:00:23 +0000
Subject: [PATCH] net/iavf: fix Rx queue interrupt setting
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit a08f9cb698c3d4687765860e328dca727f7a516b ]

For Rx-Queue Interrupt Setting, when VF Rx interrupt
disable (INTENA=0), there are two ways to write back
descriptor to host memory:

1) Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register:
Completed descriptors are posted to host memory according to
the internal descriptor cache policy (in other words when a
full cache line is available for write-back).

A internal descriptor size is 16 bytes or 32 bytes, a cache
line size is 64 bytes or 128 bytes from datasheet :
PCIe Global Config 2 - GLPCI_CNF2 (0x000BE004; RO)
so the full cache line could contains 4 packets, it means
Network card will send 4 packets to host when a full cache line
is available.

2) Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register:
Completed descriptors also trigger the ITR. Following ITR
expiration, all leftover completed descriptors are posted to
host memory.

Network card will send packet to host even if only one
descriptor is completed.

Changing 1) to 2) to make sure VF send the packet to host even
if there is only one Rx packet is ready in hardware.

Fixes: d6bde6b5eae9 ("net/avf: enable Rx interrupt")

Signed-off-by: Ke Zhang <ke1x.zhang at intel.com>
Acked-by: Qi Zhang <qi.z.zhang at intel.com>
---
 drivers/net/iavf/iavf_ethdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index bbbd7e84a4..060b3e3707 100644
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -1431,7 +1431,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
 
 	IAVF_WRITE_REG(hw,
 		      IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
-		      0);
+		      IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
 
 	IAVF_WRITE_FLUSH(hw);
 	return 0;
-- 
2.35.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2022-06-21 15:37:53.696163186 +0800
+++ 0100-net-iavf-fix-Rx-queue-interrupt-setting.patch	2022-06-21 15:37:49.214451878 +0800
@@ -1 +1 @@
-From a08f9cb698c3d4687765860e328dca727f7a516b Mon Sep 17 00:00:00 2001
+From 789223ef41ebf4a8b9efecf516cb415f2bf48cf0 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit a08f9cb698c3d4687765860e328dca727f7a516b ]
@@ -34 +36,0 @@
-Cc: stable at dpdk.org
@@ -43 +45 @@
-index 315ab15aad..a74056f0f1 100644
+index bbbd7e84a4..060b3e3707 100644
@@ -46 +48 @@
-@@ -1925,7 +1925,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
+@@ -1431,7 +1431,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)