[PATCH 3/7] net/txgbe: fix register polling
Ferruh Yigit
ferruh.yigit at xilinx.com
Tue Jun 21 14:19:27 CEST 2022
On 6/20/2022 8:55 AM, Jiawen Wu wrote:
> Fix to poll some specific registers, which expect bit 0.
>
> Fixes: 24a4c76aff4d ("net/txgbe: add error types and registers")
> Cc: stable at dpdk.org
>
> Signed-off-by: Jiawen Wu <jiawenwu at trustnetic.com>
> ---
> drivers/net/txgbe/base/txgbe_regs.h | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h
> index 3139796911..911bb6e04e 100644
> --- a/drivers/net/txgbe/base/txgbe_regs.h
> +++ b/drivers/net/txgbe/base/txgbe_regs.h
> @@ -1864,8 +1864,13 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,
> }
>
> do {
> - all |= rd32(hw, reg);
> - value |= mask & all;
> + if (expect != 0) {
> + all |= rd32(hw, reg);
> + value |= mask & all;
> + } else {
> + all = rd32(hw, reg);
> + value = mask & all;
> + }
> if (value == expect)
> break;
>
> @@ -1898,7 +1903,7 @@ po32m(struct txgbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,
>
> #define wr32w(hw, reg, val, mask, slice) do { \
> wr32((hw), reg, val); \
> - po32m((hw), reg, mask, mask, NULL, 5, slice); \
> + po32m((hw), reg, mask, 0, NULL, 5, slice); \
Just to double check, is this change intentional, to always expect
reading '0' from registers after writing to them?
Perhaps you can explain a little more about this polling after
read/write logic and what was wrong in the commit log.
> } while (0)
>
> #define TXGBE_XPCS_IDAADDR 0x13000
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