patch 'net/mlx5: fix available tag registers calculation for HWS' has been queued to stable release 22.11.2

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 22.11.2

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 03/01/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=dcb16c48e0bda0839c1cc1ad6e955a290614d69b

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From dcb16c48e0bda0839c1cc1ad6e955a290614d69b Mon Sep 17 00:00:00 2001
From: Dariusz Sosnowski <dsosnowski at nvidia.com>
Date: Tue, 22 Nov 2022 12:53:20 +0000
Subject: [PATCH] net/mlx5: fix available tag registers calculation for HWS
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 1888b455dfe2b31d09fbce61e671507313ed451e ]

Before this patch, if two ports in separate switch domains
were probed by an application, the shared array of available TAG
registers was calculated incorrectly.

When the intersection of supported REG_C registers and
available TAG registers was calculated,
capabilities were checked against an index of the TAG array,
not the register stored under that index.

This patch fixes this behavior by comparing capabilities mask
against registers stored in the TAG array.
Available TAG registers calculation is also refactored
to simplify the code.

Fixes: 8a89038f40ca ("net/mlx5: provide available tag registers")

Signed-off-by: Dariusz Sosnowski <dsosnowski at nvidia.com>
Reviewed-by: Bing Zhao <bingz at nvidia.com>
Acked-by: Ori Kam <orika at nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_hw.c | 46 +++++++++++++++++++--------------
 1 file changed, 26 insertions(+), 20 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index a3c8056515..20c71ff7f0 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -7178,9 +7178,9 @@ void flow_hw_init_tags_set(struct rte_eth_dev *dev)
 	uint32_t meta_mode = priv->sh->config.dv_xmeta_en;
 	uint8_t masks = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;
 	uint32_t i, j;
-	enum modify_reg copy[MLX5_FLOW_HW_TAGS_MAX] = {REG_NON};
+	uint8_t reg_off;
 	uint8_t unset = 0;
-	uint8_t copy_masks = 0;
+	uint8_t common_masks = 0;

 	/*
 	 * The CAPA is global for common device but only used in net.
@@ -7195,29 +7195,35 @@ void flow_hw_init_tags_set(struct rte_eth_dev *dev)
 	if (meta_mode == MLX5_XMETA_MODE_META32_HWS)
 		unset |= 1 << (REG_C_1 - REG_C_0);
 	masks &= ~unset;
+	/*
+	 * If available tag registers were previously calculated,
+	 * calculate a bitmask with an intersection of sets of:
+	 * - registers supported by current port,
+	 * - previously calculated available tag registers.
+	 */
 	if (mlx5_flow_hw_avl_tags_init_cnt) {
 		MLX5_ASSERT(mlx5_flow_hw_aso_tag == priv->mtr_color_reg);
 		for (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {
-			if (mlx5_flow_hw_avl_tags[i] != REG_NON && !!((1 << i) & masks)) {
-				copy[mlx5_flow_hw_avl_tags[i] - REG_C_0] =
-						mlx5_flow_hw_avl_tags[i];
-				copy_masks |= (1 << (mlx5_flow_hw_avl_tags[i] - REG_C_0));
-			}
-		}
-		if (copy_masks != masks) {
-			j = 0;
-			for (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++)
-				if (!!((1 << i) & copy_masks))
-					mlx5_flow_hw_avl_tags[j++] = copy[i];
-		}
-	} else {
-		j = 0;
-		for (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {
-			if (!!((1 << i) & masks))
-				mlx5_flow_hw_avl_tags[j++] =
-					(enum modify_reg)(i + (uint32_t)REG_C_0);
+			if (mlx5_flow_hw_avl_tags[i] == REG_NON)
+				continue;
+			reg_off = mlx5_flow_hw_avl_tags[i] - REG_C_0;
+			if ((1 << reg_off) & masks)
+				common_masks |= (1 << reg_off);
 		}
+		if (common_masks != masks)
+			masks = common_masks;
+		else
+			goto after_avl_tags;
+	}
+	j = 0;
+	for (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {
+		if ((1 << i) & masks)
+			mlx5_flow_hw_avl_tags[j++] = (enum modify_reg)(i + (uint32_t)REG_C_0);
 	}
+	/* Clear the rest of unusable tag indexes. */
+	for (; j < MLX5_FLOW_HW_TAGS_MAX; j++)
+		mlx5_flow_hw_avl_tags[j] = REG_NON;
+after_avl_tags:
 	priv->sh->hws_tags = 1;
 	mlx5_flow_hw_aso_tag = (enum modify_reg)priv->mtr_color_reg;
 	mlx5_flow_hw_avl_tags_init_cnt++;
--
2.25.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-02-27 14:08:44.688866200 +0800
+++ 0119-net-mlx5-fix-available-tag-registers-calculation-for.patch	2023-02-27 14:08:40.879237000 +0800
@@ -1 +1 @@
-From 1888b455dfe2b31d09fbce61e671507313ed451e Mon Sep 17 00:00:00 2001
+From dcb16c48e0bda0839c1cc1ad6e955a290614d69b Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 1888b455dfe2b31d09fbce61e671507313ed451e ]
@@ -21 +23,0 @@
-Cc: stable at dpdk.org
@@ -31 +33 @@
-index 6893431011..2930f3b0b9 100644
+index a3c8056515..20c71ff7f0 100644
@@ -34 +36 @@
-@@ -7180,9 +7180,9 @@ void flow_hw_init_tags_set(struct rte_eth_dev *dev)
+@@ -7178,9 +7178,9 @@ void flow_hw_init_tags_set(struct rte_eth_dev *dev)
@@ -46 +48 @@
-@@ -7197,29 +7197,35 @@ void flow_hw_init_tags_set(struct rte_eth_dev *dev)
+@@ -7195,29 +7195,35 @@ void flow_hw_init_tags_set(struct rte_eth_dev *dev)