patch 'common/idpf/base: fix control queue send and receive' has been queued to stable release 22.11.3

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 22.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 06/27/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=4cc85337b399df2a47f997980ea2ac80030464d7

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From 4cc85337b399df2a47f997980ea2ac80030464d7 Mon Sep 17 00:00:00 2001
From: Wenjing Qiao <wenjing.qiao at intel.com>
Date: Wed, 26 Apr 2023 06:22:46 -0400
Subject: [PATCH] common/idpf/base: fix control queue send and receive
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit abb00ba2ad68eedbb7d04dd05ef1b112fd9211f9 ]

Fixes the ctlq send and receive functions to not cast the cookie field
to a u64 before programming. By doing a cast, it can cause endianness
issues as LE will swap the lower 32 and higher 32 bits whereas BE will
not. By treating this field as two 32 bit values, both BE and LE will
place the retval and opcode in the correct location.

Since this field is now being treated as two 32 bit values, the cfg.data
section must also be split into a data high and data low. Macros to
easily pack and read these fields have also been added.

Fixes: fb4ac04e9bfa ("common/idpf: introduce common library")

Signed-off-by: Charles Stoll <charles.stoll at intel.com>
Signed-off-by: Wenjing Qiao <wenjing.qiao at intel.com>
Acked-by: Qi Zhang <qi.z.zhang at intel.com>
---
 .mailmap                                 |  1 +
 drivers/common/idpf/base/idpf_controlq.c | 16 ++++------------
 2 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/.mailmap b/.mailmap
index 79553991de..642bb987d0 100644
--- a/.mailmap
+++ b/.mailmap
@@ -198,6 +198,7 @@ Chaoyong He <chaoyong.he at corigine.com>
 Chao Zhu <chaozhu at linux.vnet.ibm.com> <bjzhuc at cn.ibm.com>
 Charles Brett <cfb at hpe.com>
 Charles Myers <charles.myers at spirent.com>
+Charles Stoll <charles.stoll at intel.com>
 Chas Williams <3chas3 at gmail.com> <chas3 at att.com> <ciwillia at brocade.com>
 Chenbo Xia <chenbo.xia at intel.com>
 Chengchang Tang <tangchengchang at huawei.com> <tangchengchang at hisilicon.com>
diff --git a/drivers/common/idpf/base/idpf_controlq.c b/drivers/common/idpf/base/idpf_controlq.c
index 3af81e5a64..8e4d3ee54f 100644
--- a/drivers/common/idpf/base/idpf_controlq.c
+++ b/drivers/common/idpf/base/idpf_controlq.c
@@ -311,18 +311,14 @@ int idpf_ctlq_send(struct idpf_hw *hw, struct idpf_ctlq_info *cq,
 
 	for (i = 0; i < num_q_msg; i++) {
 		struct idpf_ctlq_msg *msg = &q_msg[i];
-		u64 msg_cookie;
 
 		desc = IDPF_CTLQ_DESC(cq, cq->next_to_use);
 
 		desc->opcode = CPU_TO_LE16(msg->opcode);
 		desc->pfid_vfid = CPU_TO_LE16(msg->func_id);
 
-		msg_cookie = *(u64 *)&msg->cookie;
-		desc->cookie_high =
-			CPU_TO_LE32(IDPF_HI_DWORD(msg_cookie));
-		desc->cookie_low =
-			CPU_TO_LE32(IDPF_LO_DWORD(msg_cookie));
+		desc->cookie_high = CPU_TO_LE32(msg->cookie.mbx.chnl_opcode);
+		desc->cookie_low = CPU_TO_LE32(msg->cookie.mbx.chnl_retval);
 
 		desc->flags = CPU_TO_LE16((msg->host_id & IDPF_HOST_ID_MASK) <<
 					  IDPF_CTLQ_FLAG_HOST_ID_S);
@@ -620,8 +616,6 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg,
 	num_to_clean = *num_q_msg;
 
 	for (i = 0; i < num_to_clean; i++) {
-		u64 msg_cookie;
-
 		/* Fetch next descriptor and check if marked as done */
 		desc = IDPF_CTLQ_DESC(cq, ntc);
 		flags = LE16_TO_CPU(desc->flags);
@@ -639,10 +633,8 @@ int idpf_ctlq_recv(struct idpf_ctlq_info *cq, u16 *num_q_msg,
 		if (flags & IDPF_CTLQ_FLAG_ERR)
 			ret_code = -EBADMSG;
 
-		msg_cookie = (u64)LE32_TO_CPU(desc->cookie_high) << 32;
-		msg_cookie |= (u64)LE32_TO_CPU(desc->cookie_low);
-		idpf_memcpy(&q_msg[i].cookie, &msg_cookie, sizeof(u64),
-			    IDPF_NONDMA_TO_NONDMA);
+		q_msg[i].cookie.mbx.chnl_opcode = LE32_TO_CPU(desc->cookie_high);
+		q_msg[i].cookie.mbx.chnl_retval = LE32_TO_CPU(desc->cookie_low);
 
 		q_msg[i].opcode = LE16_TO_CPU(desc->opcode);
 		q_msg[i].data_len = LE16_TO_CPU(desc->datalen);
-- 
2.25.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-06-25 14:32:01.389933100 +0800
+++ 0108-common-idpf-base-fix-control-queue-send-and-receive.patch	2023-06-25 14:31:58.555773900 +0800
@@ -1 +1 @@
-From abb00ba2ad68eedbb7d04dd05ef1b112fd9211f9 Mon Sep 17 00:00:00 2001
+From 4cc85337b399df2a47f997980ea2ac80030464d7 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit abb00ba2ad68eedbb7d04dd05ef1b112fd9211f9 ]
@@ -17 +19,0 @@
-Cc: stable at dpdk.org
@@ -28 +30 @@
-index 0431e410a7..c5fb28ad86 100644
+index 79553991de..642bb987d0 100644
@@ -31 +33 @@
-@@ -201,6 +201,7 @@ Chaoyong He <chaoyong.he at corigine.com>
+@@ -198,6 +198,7 @@ Chaoyong He <chaoyong.he at corigine.com>