patch 'common/idpf/base: fix ITR register definitions for AVF' has been queued to stable release 22.11.3

[Xueming Li]

Hi,

FYI, your patch has been queued to stable release 22.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 06/27/23. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=e5868f66487b1e7f1009e245c613b24584a1d7b5

Thanks.

Xueming Li <xuemingl at nvidia.com>

---
>From e5868f66487b1e7f1009e245c613b24584a1d7b5 Mon Sep 17 00:00:00 2001
From: Wenjing Qiao <wenjing.qiao at intel.com>
Date: Wed, 26 Apr 2023 06:22:47 -0400
Subject: [PATCH] common/idpf/base: fix ITR register definitions for AVF
Cc: Xueming Li <xuemingl at nvidia.com>

[ upstream commit 1ce244efe0765554531f450380d6c887cd92dfab ]

Fix ITR register definitions for AVF1.0 and AVF2.0

Fixes: fb4ac04e9bfa ("common/idpf: introduce common library")

Signed-off-by: Priyalee Kushwaha <priyalee.kushwaha at intel.com>
Signed-off-by: Wenjing Qiao <wenjing.qiao at intel.com>
Acked-by: Qi Zhang <qi.z.zhang at intel.com>
---
 .mailmap                                    |  1 +
 drivers/common/idpf/base/idpf_lan_pf_regs.h |  9 +++++++--
 drivers/common/idpf/base/idpf_lan_vf_regs.h | 17 ++++++++++++-----
 3 files changed, 20 insertions(+), 7 deletions(-)

diff --git a/.mailmap b/.mailmap
index 642bb987d0..6b38c488c2 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1066,6 +1066,7 @@ Prashant Upadhyaya <prashant.upadhyaya at aricent.com> <praupadhyaya at gmail.com>
 Prateek Agarwal <prateekag at cse.iitb.ac.in>
 Praveen Shetty <praveen.shetty at intel.com>
 Pravin Pathak <pravin.pathak at intel.com>
+Priyalee Kushwaha <priyalee.kushwaha at intel.com>
 Priyanka Jain <priyanka.jain at nxp.com>
 Przemyslaw Ciesielski <przemyslaw.ciesielski at intel.com>
 Przemyslaw Czesnowicz <przemyslaw.czesnowicz at intel.com>
diff --git a/drivers/common/idpf/base/idpf_lan_pf_regs.h b/drivers/common/idpf/base/idpf_lan_pf_regs.h
index 3df2347bd7..7f731ec3d6 100644
--- a/drivers/common/idpf/base/idpf_lan_pf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_pf_regs.h
@@ -77,8 +77,13 @@
 #define PF_GLINT_DYN_CTL_WB_ON_ITR_M	BIT(PF_GLINT_DYN_CTL_WB_ON_ITR_S)
 #define PF_GLINT_DYN_CTL_INTENA_MSK_S	31
 #define PF_GLINT_DYN_CTL_INTENA_MSK_M	BIT(PF_GLINT_DYN_CTL_INTENA_MSK_S)
-#define PF_GLINT_ITR_V2(_i, _reg_start) (((_i) * 4) + (_reg_start))
-#define PF_GLINT_ITR(_i, _INT) (PF_GLINT_BASE + (((_i) + 1) * 4) + ((_INT) * 0x1000))
+/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is
+ * spacing b/w itrn registers of the same vector.
+ */
+#define PF_GLINT_ITR_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \
+		((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))
+/* For PF, itrn_indx_spacing is 4 and itrn_reg_spacing is 0x1000 */
+#define PF_GLINT_ITR(_ITR, _INT) (PF_GLINT_BASE + (((_ITR) + 1) * 4) + ((_INT) * 0x1000))
 #define PF_GLINT_ITR_MAX_INDEX		2
 #define PF_GLINT_ITR_INTERVAL_S		0
 #define PF_GLINT_ITR_INTERVAL_M		MAKEMASK(0xFFF, PF_GLINT_ITR_INTERVAL_S)
diff --git a/drivers/common/idpf/base/idpf_lan_vf_regs.h b/drivers/common/idpf/base/idpf_lan_vf_regs.h
index 9cd4f757d9..13c5c5a7da 100644
--- a/drivers/common/idpf/base/idpf_lan_vf_regs.h
+++ b/drivers/common/idpf/base/idpf_lan_vf_regs.h
@@ -90,11 +90,18 @@
 #define VF_INT_DYN_CTLN_WB_ON_ITR_M	BIT(VF_INT_DYN_CTLN_WB_ON_ITR_S)
 #define VF_INT_DYN_CTLN_INTENA_MSK_S	31
 #define VF_INT_DYN_CTLN_INTENA_MSK_M	BIT(VF_INT_DYN_CTLN_INTENA_MSK_S)
-#define VF_INT_ITR0(_i)			(0x00004C00 + ((_i) * 4))
-#define VF_INT_ITRN_V2(_i, _reg_start)	((_reg_start) + (((_i)) * 4))
-#define VF_INT_ITRN(_i, _INT)		(0x00002800 + ((_i) * 4) + ((_INT) * 0x40))
-#define VF_INT_ITRN_64(_i, _INT)	(0x00002C00 + ((_i) * 4) + ((_INT) * 0x100))
-#define VF_INT_ITRN_2K(_i, _INT)	(0x00072000 + ((_i) * 4) + ((_INT) * 0x100))
+/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing
+ * b/w itrn registers of the same vector
+ */
+#define VF_INT_ITR0(_ITR)		(0x00004C00 + ((_ITR) * 4))
+#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \
+		 ((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))
+/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */
+#define VF_INT_ITRN(_INT, _ITR)	(0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))
+/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */
+#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))
+/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */
+#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))
 #define VF_INT_ITRN_MAX_INDEX		2
 #define VF_INT_ITRN_INTERVAL_S		0
 #define VF_INT_ITRN_INTERVAL_M		MAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S)
-- 
2.25.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2023-06-25 14:32:01.414887400 +0800
+++ 0109-common-idpf-base-fix-ITR-register-definitions-for-AV.patch	2023-06-25 14:31:58.565773900 +0800
@@ -1 +1 @@
-From 1ce244efe0765554531f450380d6c887cd92dfab Mon Sep 17 00:00:00 2001
+From e5868f66487b1e7f1009e245c613b24584a1d7b5 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl at nvidia.com>
+
+[ upstream commit 1ce244efe0765554531f450380d6c887cd92dfab ]
@@ -9 +11,0 @@
-Cc: stable at dpdk.org
@@ -21 +23 @@
-index c5fb28ad86..da4aad001d 100644
+index 642bb987d0..6b38c488c2 100644
@@ -24 +26,2 @@
-@@ -1085,6 +1085,7 @@ Prateek Agarwal <prateekag at cse.iitb.ac.in>
+@@ -1066,6 +1066,7 @@ Prashant Upadhyaya <prashant.upadhyaya at aricent.com> <praupadhyaya at gmail.com>
+ Prateek Agarwal <prateekag at cse.iitb.ac.in>
@@ -27 +29,0 @@
- Prince Takkar <ptakkar at marvell.com>